| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3589454
[patent_doc_number] => 05567632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method for fabricating solid state image sensor device having buried type photodiode'
[patent_app_type] => 1
[patent_app_number] => 8/137219
[patent_app_country] => US
[patent_app_date] => 1993-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 25
[patent_no_of_words] => 3068
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/567/05567632.pdf
[firstpage_image] =>[orig_patent_app_number] => 137219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/137219 | Method for fabricating solid state image sensor device having buried type photodiode | Oct 17, 1993 | Issued |
| 08/138528 | REDUCTION OF CONTAMINANT BUILDUP IN SEMICONDUCTOR APPARATUS | Oct 14, 1993 | Abandoned |
Array
(
[id] => 3480383
[patent_doc_number] => 05405787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-11
[patent_title] => 'Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions'
[patent_app_type] => 1
[patent_app_number] => 8/135649
[patent_app_country] => US
[patent_app_date] => 1993-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 43
[patent_no_of_words] => 9605
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/405/05405787.pdf
[firstpage_image] =>[orig_patent_app_number] => 135649
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/135649 | Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions | Oct 13, 1993 | Issued |
Array
(
[id] => 3520668
[patent_doc_number] => 05540782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Heat treating apparatus having heat transmission-preventing plates'
[patent_app_type] => 1
[patent_app_number] => 8/135481
[patent_app_country] => US
[patent_app_date] => 1993-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3723
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/540/05540782.pdf
[firstpage_image] =>[orig_patent_app_number] => 135481
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/135481 | Heat treating apparatus having heat transmission-preventing plates | Oct 12, 1993 | Issued |
| 08/133951 | METHOD OF MAKING AN INTEGRATED CIRCUIT BIPOLAR MEMORY CELL | Oct 7, 1993 | Abandoned |
Array
(
[id] => 3584029
[patent_doc_number] => 05496408
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Apparatus for producing compound semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/131529
[patent_app_country] => US
[patent_app_date] => 1993-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8196
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/496/05496408.pdf
[firstpage_image] =>[orig_patent_app_number] => 131529
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/131529 | Apparatus for producing compound semiconductor devices | Oct 3, 1993 | Issued |
Array
(
[id] => 3071408
[patent_doc_number] => 05364802
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'Method of making a semiconductor device with buried electrode'
[patent_app_type] => 1
[patent_app_number] => 8/130461
[patent_app_country] => US
[patent_app_date] => 1993-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 32
[patent_no_of_words] => 10438
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/364/05364802.pdf
[firstpage_image] =>[orig_patent_app_number] => 130461
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/130461 | Method of making a semiconductor device with buried electrode | Sep 30, 1993 | Issued |
Array
(
[id] => 3409934
[patent_doc_number] => 05438007
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Method of fabricating field effect transistor having polycrystalline silicon gate junction'
[patent_app_type] => 1
[patent_app_number] => 8/127767
[patent_app_country] => US
[patent_app_date] => 1993-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3544
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438007.pdf
[firstpage_image] =>[orig_patent_app_number] => 127767
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/127767 | Method of fabricating field effect transistor having polycrystalline silicon gate junction | Sep 27, 1993 | Issued |
Array
(
[id] => 3425173
[patent_doc_number] => 05416031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-16
[patent_title] => 'Method of producing Bi-CMOS transistors'
[patent_app_type] => 1
[patent_app_number] => 8/127507
[patent_app_country] => US
[patent_app_date] => 1993-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 5929
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/416/05416031.pdf
[firstpage_image] =>[orig_patent_app_number] => 127507
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/127507 | Method of producing Bi-CMOS transistors | Sep 27, 1993 | Issued |
Array
(
[id] => 3454090
[patent_doc_number] => 05441571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-15
[patent_title] => 'Cylindrical apparatus for growth of epitaxial layers'
[patent_app_type] => 1
[patent_app_number] => 8/127729
[patent_app_country] => US
[patent_app_date] => 1993-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2674
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/441/05441571.pdf
[firstpage_image] =>[orig_patent_app_number] => 127729
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/127729 | Cylindrical apparatus for growth of epitaxial layers | Sep 27, 1993 | Issued |
Array
(
[id] => 3450124
[patent_doc_number] => 05385848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Method for fabricating an interconnected array of semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/123169
[patent_app_country] => US
[patent_app_date] => 1993-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 4987
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 560
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/385/05385848.pdf
[firstpage_image] =>[orig_patent_app_number] => 123169
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/123169 | Method for fabricating an interconnected array of semiconductor devices | Sep 19, 1993 | Issued |
Array
(
[id] => 3481890
[patent_doc_number] => 05445974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Method of fabricating a high-voltage, vertical-trench semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/120147
[patent_app_country] => US
[patent_app_date] => 1993-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1839
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/445/05445974.pdf
[firstpage_image] =>[orig_patent_app_number] => 120147
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/120147 | Method of fabricating a high-voltage, vertical-trench semiconductor device | Sep 9, 1993 | Issued |
Array
(
[id] => 3568213
[patent_doc_number] => 05497727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Cooling element for a semiconductor fabrication chamber'
[patent_app_type] => 1
[patent_app_number] => 8/118362
[patent_app_country] => US
[patent_app_date] => 1993-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 4118
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497727.pdf
[firstpage_image] =>[orig_patent_app_number] => 118362
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/118362 | Cooling element for a semiconductor fabrication chamber | Sep 6, 1993 | Issued |
Array
(
[id] => 3111928
[patent_doc_number] => 05395774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Methods for forming a transistor having an emitter with enhanced efficiency'
[patent_app_type] => 1
[patent_app_number] => 8/123157
[patent_app_country] => US
[patent_app_date] => 1993-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 1401
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/395/05395774.pdf
[firstpage_image] =>[orig_patent_app_number] => 123157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/123157 | Methods for forming a transistor having an emitter with enhanced efficiency | Sep 6, 1993 | Issued |
Array
(
[id] => 3606945
[patent_doc_number] => 05534073
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Semiconductor producing apparatus comprising wafer vacuum chucking device'
[patent_app_type] => 1
[patent_app_number] => 8/116968
[patent_app_country] => US
[patent_app_date] => 1993-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 64
[patent_no_of_words] => 21914
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/534/05534073.pdf
[firstpage_image] =>[orig_patent_app_number] => 116968
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/116968 | Semiconductor producing apparatus comprising wafer vacuum chucking device | Sep 6, 1993 | Issued |
Array
(
[id] => 3585924
[patent_doc_number] => 05520743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Processing apparatus with means for rotating an object mounting means and a disk body located in the mounting means differently relative to each other'
[patent_app_type] => 1
[patent_app_number] => 8/114064
[patent_app_country] => US
[patent_app_date] => 1993-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3813
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/520/05520743.pdf
[firstpage_image] =>[orig_patent_app_number] => 114064
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/114064 | Processing apparatus with means for rotating an object mounting means and a disk body located in the mounting means differently relative to each other | Aug 30, 1993 | Issued |
Array
(
[id] => 3459867
[patent_doc_number] => 05391502
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Per-wafer method for globally stressing gate oxide during device fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/113497
[patent_app_country] => US
[patent_app_date] => 1993-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 3488
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/391/05391502.pdf
[firstpage_image] =>[orig_patent_app_number] => 113497
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113497 | Per-wafer method for globally stressing gate oxide during device fabrication | Aug 26, 1993 | Issued |
Array
(
[id] => 3549618
[patent_doc_number] => 05571744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Defect free CMOS process'
[patent_app_type] => 1
[patent_app_number] => 8/113787
[patent_app_country] => US
[patent_app_date] => 1993-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 2426
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/571/05571744.pdf
[firstpage_image] =>[orig_patent_app_number] => 113787
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113787 | Defect free CMOS process | Aug 26, 1993 | Issued |
Array
(
[id] => 3441836
[patent_doc_number] => 05466615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application'
[patent_app_type] => 1
[patent_app_number] => 8/108225
[patent_app_country] => US
[patent_app_date] => 1993-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3236
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/466/05466615.pdf
[firstpage_image] =>[orig_patent_app_number] => 108225
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/108225 | Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application | Aug 18, 1993 | Issued |
Array
(
[id] => 3539274
[patent_doc_number] => 05480815
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Method of manufacturing a biopolar transistor in which an emitter region is formed by impurities supplied from double layered polysilicon'
[patent_app_type] => 1
[patent_app_number] => 8/108291
[patent_app_country] => US
[patent_app_date] => 1993-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3523
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/480/05480815.pdf
[firstpage_image] =>[orig_patent_app_number] => 108291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/108291 | Method of manufacturing a biopolar transistor in which an emitter region is formed by impurities supplied from double layered polysilicon | Aug 18, 1993 | Issued |