Search

Kevin L. Lee

Examiner (ID: 14152, Phone: (571)272-4915 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3407, 3727, 2899
Total Applications
3737
Issued Applications
3236
Pending Applications
189
Abandoned Applications
321

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4000521 [patent_doc_number] => 05858827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method of manufacturing MOS transistor device with improved threshold value control and reduced reverse short channel effect' [patent_app_type] => 1 [patent_app_number] => 8/863868 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858827.pdf [firstpage_image] =>[orig_patent_app_number] => 863868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863868
Method of manufacturing MOS transistor device with improved threshold value control and reduced reverse short channel effect May 26, 1997 Issued
Array ( [id] => 4184040 [patent_doc_number] => 06037634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Semiconductor device with first and second elements formed on first and second portions' [patent_app_type] => 1 [patent_app_number] => 8/861058 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 11679 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037634.pdf [firstpage_image] =>[orig_patent_app_number] => 861058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861058
Semiconductor device with first and second elements formed on first and second portions May 20, 1997 Issued
Array ( [id] => 3993095 [patent_doc_number] => 05985677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable' [patent_app_type] => 1 [patent_app_number] => 8/861399 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5355 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985677.pdf [firstpage_image] =>[orig_patent_app_number] => 861399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861399
Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable May 20, 1997 Issued
Array ( [id] => 4029182 [patent_doc_number] => 05994167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of making a fiberglass reinforced resin plate' [patent_app_type] => 1 [patent_app_number] => 8/861391 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1500 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994167.pdf [firstpage_image] =>[orig_patent_app_number] => 861391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861391
Method of making a fiberglass reinforced resin plate May 20, 1997 Issued
Array ( [id] => 3769824 [patent_doc_number] => 05756374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Compound semiconductor light emitting device and method of preparing the same' [patent_app_type] => 1 [patent_app_number] => 8/856911 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5874 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/756/05756374.pdf [firstpage_image] =>[orig_patent_app_number] => 856911 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856911
Compound semiconductor light emitting device and method of preparing the same May 14, 1997 Issued
Array ( [id] => 4058503 [patent_doc_number] => 05913103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method of detecting metal contaminants in a wet chemical using enhanced semiconductor growth phenomena' [patent_app_type] => 1 [patent_app_number] => 8/855515 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 2488 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913103.pdf [firstpage_image] =>[orig_patent_app_number] => 855515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855515
Method of detecting metal contaminants in a wet chemical using enhanced semiconductor growth phenomena May 12, 1997 Issued
Array ( [id] => 3937188 [patent_doc_number] => 05981328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of forming a high load resistance type static random access memory cell' [patent_app_type] => 1 [patent_app_number] => 8/854489 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2433 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981328.pdf [firstpage_image] =>[orig_patent_app_number] => 854489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854489
Method of forming a high load resistance type static random access memory cell May 11, 1997 Issued
Array ( [id] => 3931436 [patent_doc_number] => 05952671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Small electrode for a chalcogenide switching device and method for fabricating same' [patent_app_type] => 1 [patent_app_number] => 8/854220 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5167 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952671.pdf [firstpage_image] =>[orig_patent_app_number] => 854220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854220
Small electrode for a chalcogenide switching device and method for fabricating same May 8, 1997 Issued
Array ( [id] => 4030627 [patent_doc_number] => 05963784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/853853 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5042 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963784.pdf [firstpage_image] =>[orig_patent_app_number] => 853853 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853853
Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device May 8, 1997 Issued
Array ( [id] => 4116544 [patent_doc_number] => 06071768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection' [patent_app_type] => 1 [patent_app_number] => 8/852969 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2494 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071768.pdf [firstpage_image] =>[orig_patent_app_number] => 852969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852969
Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection May 7, 1997 Issued
Array ( [id] => 4070271 [patent_doc_number] => 06069017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method for real-time in-line testing of semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/853171 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5435 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069017.pdf [firstpage_image] =>[orig_patent_app_number] => 853171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853171
Method for real-time in-line testing of semiconductor wafers May 7, 1997 Issued
Array ( [id] => 4004238 [patent_doc_number] => 05960286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method of manufacturing power semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/848187 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 7536 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960286.pdf [firstpage_image] =>[orig_patent_app_number] => 848187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848187
Method of manufacturing power semiconductor devices Apr 28, 1997 Issued
Array ( [id] => 4070117 [patent_doc_number] => 05970324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Methods of making dual gated power electronic switching devices' [patent_app_type] => 1 [patent_app_number] => 8/847615 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 8736 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970324.pdf [firstpage_image] =>[orig_patent_app_number] => 847615 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847615
Methods of making dual gated power electronic switching devices Apr 27, 1997 Issued
Array ( [id] => 3947095 [patent_doc_number] => 05981982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Dual gated power electronic switching devices' [patent_app_type] => 1 [patent_app_number] => 8/847614 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 8727 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981982.pdf [firstpage_image] =>[orig_patent_app_number] => 847614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847614
Dual gated power electronic switching devices Apr 27, 1997 Issued
Array ( [id] => 4138805 [patent_doc_number] => 06060330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of customizing integrated circuits by selective secondary deposition of interconnect material' [patent_app_type] => 1 [patent_app_number] => 8/846163 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 54 [patent_no_of_words] => 8621 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060330.pdf [firstpage_image] =>[orig_patent_app_number] => 846163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846163
Method of customizing integrated circuits by selective secondary deposition of interconnect material Apr 24, 1997 Issued
Array ( [id] => 4038640 [patent_doc_number] => 05926691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Methods of fabricating borophosphosilicate glass (BPSG) films having impurity concentrations which remain stable over time, and for using such films testing of microelectronic devices' [patent_app_type] => 1 [patent_app_number] => 8/846083 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1709 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926691.pdf [firstpage_image] =>[orig_patent_app_number] => 846083 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846083
Methods of fabricating borophosphosilicate glass (BPSG) films having impurity concentrations which remain stable over time, and for using such films testing of microelectronic devices Apr 24, 1997 Issued
Array ( [id] => 4050079 [patent_doc_number] => 05943548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method of analyzing a wafer in a semiconductor device fabrication process' [patent_app_type] => 1 [patent_app_number] => 8/842271 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943548.pdf [firstpage_image] =>[orig_patent_app_number] => 842271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842271
Method of analyzing a wafer in a semiconductor device fabrication process Apr 23, 1997 Issued
Array ( [id] => 4003804 [patent_doc_number] => 05960255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Calibration standard for 2-D and 3-D profilometry in the sub-nanometer range and method of producing it' [patent_app_type] => 1 [patent_app_number] => 8/842307 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2745 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960255.pdf [firstpage_image] =>[orig_patent_app_number] => 842307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842307
Calibration standard for 2-D and 3-D profilometry in the sub-nanometer range and method of producing it Apr 23, 1997 Issued
Array ( [id] => 3968427 [patent_doc_number] => 05904491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Planar waveguides' [patent_app_type] => 1 [patent_app_number] => 8/842021 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904491.pdf [firstpage_image] =>[orig_patent_app_number] => 842021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842021
Planar waveguides Apr 22, 1997 Issued
Array ( [id] => 3768616 [patent_doc_number] => 05849605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Two-phase clock type charge coupled device having electrodes with tapered sidewalls and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/844653 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 8949 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/849/05849605.pdf [firstpage_image] =>[orig_patent_app_number] => 844653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844653
Two-phase clock type charge coupled device having electrodes with tapered sidewalls and method for producing the same Apr 20, 1997 Issued
Menu