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Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19515809 [patent_doc_number] => 20240347495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD [patent_app_type] => utility [patent_app_number] => 18/752274 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752274
METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD Jun 23, 2024 Pending
Array ( [id] => 20553017 [patent_doc_number] => 12563827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor device including a field effect transistor and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/744905 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 41 [patent_no_of_words] => 8311 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744905
Semiconductor device including a field effect transistor and method of fabricating the same Jun 16, 2024 Issued
Array ( [id] => 19407928 [patent_doc_number] => 20240291439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => POWER AMPLIFIER MODULES INCLUDING TOPSIDE COOLING INTERFACES AND METHODS FOR THE FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/637486 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637486
POWER AMPLIFIER MODULES INCLUDING TOPSIDE COOLING INTERFACES AND METHODS FOR THE FABRICATION THEREOF Apr 16, 2024 Issued
Array ( [id] => 20144325 [patent_doc_number] => 12378656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Alloy metal plate and deposition mask including alloy metal plate [patent_app_type] => utility [patent_app_number] => 18/632822 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 15282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632822
Alloy metal plate and deposition mask including alloy metal plate Apr 10, 2024 Issued
Array ( [id] => 19381411 [patent_doc_number] => 20240271281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DEPOSITION OF METAL FILMS [patent_app_type] => utility [patent_app_number] => 18/626278 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626278
DEPOSITION OF METAL FILMS Apr 2, 2024 Pending
Array ( [id] => 19285800 [patent_doc_number] => 20240222277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD FOR MANUFACTURING INTEGRATED SUBSTRATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/610286 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610286
METHOD FOR MANUFACTURING INTEGRATED SUBSTRATE STRUCTURE Mar 19, 2024 Pending
Array ( [id] => 19285770 [patent_doc_number] => 20240222247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK [patent_app_type] => utility [patent_app_number] => 18/604613 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604613
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK Mar 13, 2024 Pending
Array ( [id] => 19435995 [patent_doc_number] => 20240304493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD FOR MAKING RADIO FREQUENCY SILICON-ON-INSULATOR (RFSOI) STRUCTURE INCLUDING A SUPERLATTICE [patent_app_type] => utility [patent_app_number] => 18/598321 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598321
METHOD FOR MAKING RADIO FREQUENCY SILICON-ON-INSULATOR (RFSOI) STRUCTURE INCLUDING A SUPERLATTICE Mar 6, 2024 Pending
Array ( [id] => 19285740 [patent_doc_number] => 20240222217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING HIGH THERMAL CONDUCTIVITY LAYER [patent_app_type] => utility [patent_app_number] => 18/593381 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593381
SEMICONDUCTOR PACKAGE INCLUDING HIGH THERMAL CONDUCTIVITY LAYER Feb 29, 2024 Pending
Array ( [id] => 19252966 [patent_doc_number] => 20240203963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SYSTEMS AND METHODS FOR REDUCING THE SIZE OF A SEMICONDUCTOR ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/588595 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588595
SYSTEMS AND METHODS FOR REDUCING THE SIZE OF A SEMICONDUCTOR ASSEMBLY Feb 26, 2024 Pending
Array ( [id] => 20259003 [patent_doc_number] => 12431366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Structure having thermal dissipation structure therein and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/442033 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 10451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442033
Structure having thermal dissipation structure therein and manufacturing method thereof Feb 13, 2024 Issued
Array ( [id] => 19191495 [patent_doc_number] => 20240170408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR PACKAGE WITH STEPPED REDISTRIBUTION STRUCTURE EXPOSING MOLD LAYER [patent_app_type] => utility [patent_app_number] => 18/426995 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426995
SEMICONDUCTOR PACKAGE WITH STEPPED REDISTRIBUTION STRUCTURE EXPOSING MOLD LAYER Jan 29, 2024 Pending
Array ( [id] => 19252948 [patent_doc_number] => 20240203945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/419399 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419399
SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF Jan 21, 2024 Pending
Array ( [id] => 20089039 [patent_doc_number] => 20250218975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => WAFER-LEVEL CHIP SCALE PACKAGE SEMICONDUCTOR DEVICES WITH LIGHT BLOCKING MATERIAL AND METHODS [patent_app_type] => utility [patent_app_number] => 18/399630 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399630
WAFER-LEVEL CHIP SCALE PACKAGE SEMICONDUCTOR DEVICES WITH LIGHT BLOCKING MATERIAL AND METHODS Dec 27, 2023 Pending
Array ( [id] => 19038235 [patent_doc_number] => 20240088050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Chamfered Die of Semiconductor Package and Method for Forming the Same [patent_app_type] => utility [patent_app_number] => 18/514126 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514126
Chamfered Die of Semiconductor Package and Method for Forming the Same Nov 19, 2023 Pending
Array ( [id] => 20230428 [patent_doc_number] => 12419093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Structure of flash memory cell [patent_app_type] => utility [patent_app_number] => 18/504165 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504165
Structure of flash memory cell Nov 7, 2023 Issued
Array ( [id] => 19886940 [patent_doc_number] => 12272672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor device with hollow interconnectors [patent_app_type] => utility [patent_app_number] => 18/386349 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 10629 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386349
Semiconductor device with hollow interconnectors Nov 1, 2023 Issued
Array ( [id] => 19688003 [patent_doc_number] => 20250006548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => FIELD EFFECT TRANSISTOR WITH DUAL LAYER ISOLATION STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/499908 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499908
FIELD EFFECT TRANSISTOR WITH DUAL LAYER ISOLATION STRUCTURE AND METHOD Oct 31, 2023 Pending
Array ( [id] => 19589926 [patent_doc_number] => 20240387483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/493041 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493041
SEMICONDUCTOR PACKAGE Oct 23, 2023 Pending
Array ( [id] => 18977231 [patent_doc_number] => 20240057323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH BURIED CONTACTS AND A FENCE [patent_app_type] => utility [patent_app_number] => 18/492105 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492105
Semiconductor memory device with buried contacts and a fence Oct 22, 2023 Issued
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