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Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18975245 [patent_doc_number] => 20240055337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/309113 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309113
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Apr 27, 2023 Pending
Array ( [id] => 18743463 [patent_doc_number] => 20230352451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => THREE-DIMENSIONAL FAN-OUT MEMORY POP STRUCTURE AND PACKAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/139748 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139748
THREE-DIMENSIONAL FAN-OUT MEMORY POP STRUCTURE AND PACKAGING METHOD THEREOF Apr 25, 2023 Pending
Array ( [id] => 19546540 [patent_doc_number] => 20240363576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/307002 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307002
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME Apr 24, 2023 Pending
Array ( [id] => 18848951 [patent_doc_number] => 20230411355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/138564 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138564 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138564
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Apr 23, 2023 Pending
Array ( [id] => 19515689 [patent_doc_number] => 20240347375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING ISOLATION STRUCTURE WITH IMPURITY AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/135350 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135350
SEMICONDUCTOR DEVICE INCLUDING ISOLATION STRUCTURE WITH IMPURITY AND METHOD FOR MANUFACTURING THE SAME Apr 16, 2023 Pending
Array ( [id] => 18555326 [patent_doc_number] => 20230253343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/301606 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301606
Semiconductor package with dummy pattern not electrically connected to circuit pattern Apr 16, 2023 Issued
Array ( [id] => 19515746 [patent_doc_number] => 20240347432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => CONFIGURABLE WARPAGE CONTROL SPACERS [patent_app_type] => utility [patent_app_number] => 18/298645 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298645
CONFIGURABLE WARPAGE CONTROL SPACERS Apr 10, 2023 Pending
Array ( [id] => 18696432 [patent_doc_number] => 20230326871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/131258 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/131258
SEMICONDUCTOR PACKAGE Apr 4, 2023 Pending
Array ( [id] => 18729393 [patent_doc_number] => 20230343689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => 3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR [patent_app_type] => utility [patent_app_number] => 18/129840 [patent_app_country] => US [patent_app_date] => 2023-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 137013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18129840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/129840
3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR Mar 31, 2023 Pending
Array ( [id] => 19483993 [patent_doc_number] => 20240332035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Semiconductor Device and Method of Forming Interconnect Structure with Graphene Core Shells for 3D Stacking Package [patent_app_type] => utility [patent_app_number] => 18/193942 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193942 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193942
Semiconductor Device and Method of Forming Interconnect Structure with Graphene Core Shells for 3D Stacking Package Mar 30, 2023 Pending
Array ( [id] => 19486637 [patent_doc_number] => 20240334679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY CELL WITH REDUCED PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 18/127774 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127774
MEMORY CELL WITH REDUCED PARASITIC CAPACITANCE Mar 28, 2023 Pending
Array ( [id] => 18514664 [patent_doc_number] => 20230230925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => FACE-TO-FACE DIES WITH A VOID FOR ENHANCED INDUCTOR PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/190747 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190747
FACE-TO-FACE DIES WITH A VOID FOR ENHANCED INDUCTOR PERFORMANCE Mar 26, 2023 Pending
Array ( [id] => 18500552 [patent_doc_number] => 20230223346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/125177 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125177
Semiconductor device with stacked structure Mar 22, 2023 Issued
Array ( [id] => 18586001 [patent_doc_number] => 20230268266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/186618 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186618 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186618
Fan-out semiconductor package and electronic device including the same Mar 19, 2023 Issued
Array ( [id] => 18440114 [patent_doc_number] => 20230187409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/166493 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166493
Multi-chip package and manufacturing method thereof Feb 8, 2023 Issued
Array ( [id] => 19056994 [patent_doc_number] => 20240098963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Semiconductor Structure and Method Making the Same [patent_app_type] => utility [patent_app_number] => 18/163072 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163072
Semiconductor Structure and Method Making the Same Jan 31, 2023 Issued
Array ( [id] => 19337116 [patent_doc_number] => 20240251546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => DRAM Transistor Including Pillars Formed Using Low-Temperature Ion Implant [patent_app_type] => utility [patent_app_number] => 18/100289 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100289
DRAM Transistor Including Pillars Formed Using Low-Temperature Ion Implant Jan 22, 2023 Pending
Array ( [id] => 18535006 [patent_doc_number] => 20230240087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => INTEGRATED SCALING AND STRETCHING PLATFORM FOR SERVER PROCESSOR AND RACK SERVER UNIT [patent_app_type] => utility [patent_app_number] => 18/099677 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099677 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099677
INTEGRATED SCALING AND STRETCHING PLATFORM FOR SERVER PROCESSOR AND RACK SERVER UNIT Jan 19, 2023 Pending
Array ( [id] => 19323280 [patent_doc_number] => 20240244828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/155043 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155043
MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF Jan 15, 2023 Pending
Array ( [id] => 18884879 [patent_doc_number] => 20240008248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/154756 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154756
METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Jan 12, 2023 Pending
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