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Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20260532 [patent_doc_number] => 12432903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor structure and method for fabricating same [patent_app_type] => utility [patent_app_number] => 18/152168 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2243 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152168
Semiconductor structure and method for fabricating same Jan 9, 2023 Issued
Array ( [id] => 19460184 [patent_doc_number] => 12100693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => RGB LED package with BSY emitter [patent_app_type] => utility [patent_app_number] => 18/067186 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 6858 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067186
RGB LED package with BSY emitter Dec 15, 2022 Issued
Array ( [id] => 18312918 [patent_doc_number] => 20230116818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => PACKAGE HAVING MULTIPLE CHIPS INTEGRATED THEREIN AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/080661 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080661
Package having multiple chips integrated therein and manufacturing method thereof Dec 12, 2022 Issued
Array ( [id] => 20553266 [patent_doc_number] => 12564081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Electronic device and semiconductor device with wiring froups for parallel signal transmission [patent_app_type] => utility [patent_app_number] => 18/074265 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5793 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18074265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/074265
Electronic device and semiconductor device with wiring froups for parallel signal transmission Dec 1, 2022 Issued
Array ( [id] => 19206281 [patent_doc_number] => 20240178180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/072096 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072096
SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR DEVICES Nov 29, 2022 Pending
Array ( [id] => 18408930 [patent_doc_number] => 20230170283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/070966 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070966
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE Nov 28, 2022 Pending
Array ( [id] => 18572623 [patent_doc_number] => 20230262961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/957242 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957242
SEMICONDUCTOR MEMORY DEVICE Sep 29, 2022 Pending
Array ( [id] => 18425987 [patent_doc_number] => 20230180452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/956102 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956102
Semiconductor memory device Sep 28, 2022 Issued
Array ( [id] => 18143092 [patent_doc_number] => 20230016938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/934551 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934551
Semiconductor structure with semiconductor pillars and method for manufacturing same Sep 21, 2022 Issued
Array ( [id] => 19054876 [patent_doc_number] => 20240096845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => CIRCUIT PACKAGES WITH BUMP INTERCONNECT POLYMER SURROUND AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/934023 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934023
CIRCUIT PACKAGES WITH BUMP INTERCONNECT POLYMER SURROUND AND METHOD OF MANUFACTURE Sep 20, 2022 Pending
Array ( [id] => 18633568 [patent_doc_number] => 20230292495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/947606 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947606
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Sep 18, 2022 Abandoned
Array ( [id] => 19010066 [patent_doc_number] => 20240074137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 17/822390 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822390
CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION Aug 24, 2022 Pending
Array ( [id] => 18061712 [patent_doc_number] => 20220392799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => TRENCH ISOLATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/818497 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818497
Trench isolation process Aug 8, 2022 Issued
Array ( [id] => 18475520 [patent_doc_number] => 20230209808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/880723 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880723
SEMICONDUCTOR DEVICE Aug 3, 2022 Pending
Array ( [id] => 20509020 [patent_doc_number] => 12543312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor memory device including a charge storage layer [patent_app_type] => utility [patent_app_number] => 17/879874 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 7237 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879874
Semiconductor memory device including a charge storage layer Aug 2, 2022 Issued
Array ( [id] => 19460145 [patent_doc_number] => 12100652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Multilevel interconnection structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/874982 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 7239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874982
Multilevel interconnection structure and method for forming the same Jul 26, 2022 Issued
Array ( [id] => 19980240 [patent_doc_number] => 12347728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Bi-layer alloy liner for interconnect metallization and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/873941 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873941
Bi-layer alloy liner for interconnect metallization and methods of forming the same Jul 25, 2022 Issued
Array ( [id] => 19341476 [patent_doc_number] => 12051673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Package having multiple chips integrated therein and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/872013 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 14338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872013
Package having multiple chips integrated therein and manufacturing method thereof Jul 24, 2022 Issued
Array ( [id] => 18929274 [patent_doc_number] => 20240032278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/814235 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814235
Memory structure including low dielectric constant capping layer Jul 21, 2022 Issued
Array ( [id] => 18774564 [patent_doc_number] => 20230369395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 17/814056 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814056
Semiconductor device with offset source/drain regions and methods of formation Jul 20, 2022 Issued
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