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Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17780232 [patent_doc_number] => 20220246582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/495612 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495612
SEMICONDUCTOR PACKAGE Oct 5, 2021 Abandoned
Array ( [id] => 17566665 [patent_doc_number] => 20220130814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => LAND-SIDE SILICON CAPACITOR DESIGN AND SEMICONDUCTOR PACKAGE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/494851 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494851
Land-side silicon capacitor design and semiconductor package using the same Oct 5, 2021 Issued
Array ( [id] => 17373866 [patent_doc_number] => 20220028918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 17/494202 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494202
Imaging device including multiple photoelectric conversion layers, multiple pixel electrodes and plugs connecting substrate and the pixel electrodes Oct 4, 2021 Issued
Array ( [id] => 18798574 [patent_doc_number] => 11832442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor memory device with buried contacts and a fence [patent_app_type] => utility [patent_app_number] => 17/493671 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8889 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493671
Semiconductor memory device with buried contacts and a fence Oct 3, 2021 Issued
Array ( [id] => 17536791 [patent_doc_number] => 20220115400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => NAND FLASH MEMORY AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/489826 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489826
NAND flash memory and manufacturing method thereof Sep 29, 2021 Issued
Array ( [id] => 17933633 [patent_doc_number] => 20220328759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/489352 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489352
Magnetic random access memory and manufacturing method thereof Sep 28, 2021 Issued
Array ( [id] => 18284756 [patent_doc_number] => 20230100228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS [patent_app_type] => utility [patent_app_number] => 17/485217 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485217
PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS Sep 23, 2021 Pending
Array ( [id] => 18255587 [patent_doc_number] => 20230082626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHOD FOR UNDERFILLING USING SPACERS [patent_app_type] => utility [patent_app_number] => 17/474674 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474674
Method for underfilling using spacers Sep 13, 2021 Issued
Array ( [id] => 17795689 [patent_doc_number] => 20220254781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/468139 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468139
Semiconductor device including a field effect transistor and method of fabricating the same Sep 6, 2021 Issued
Array ( [id] => 18238557 [patent_doc_number] => 20230070868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => INTEGRATED ISOLATOR INCORPORATING TRENCH CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/467564 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467564
Integrated isolator incorporating trench capacitor Sep 6, 2021 Issued
Array ( [id] => 17855488 [patent_doc_number] => 20220285531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => ISOLATED FIN STRUCTURES IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/468483 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468483
Isolated fin structures in semiconductor devices Sep 6, 2021 Issued
Array ( [id] => 18221912 [patent_doc_number] => 20230060906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MRAM STACK WITH REDUCED HEIGHT [patent_app_type] => utility [patent_app_number] => 17/464076 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464076
MRAM stack with reduced height Aug 31, 2021 Issued
Array ( [id] => 18229584 [patent_doc_number] => 20230068578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/460321 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460321
Package structure having thermal dissipation structure therein and manufacturing method thereof Aug 29, 2021 Issued
Array ( [id] => 17855397 [patent_doc_number] => 20220285440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/459042 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459042
SEMICONDUCTOR STORAGE DEVICE Aug 26, 2021 Abandoned
Array ( [id] => 19123553 [patent_doc_number] => 11967547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Solder resist structure to mitigate solder bridge risk [patent_app_type] => utility [patent_app_number] => 17/412641 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 36 [patent_no_of_words] => 8590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412641
Solder resist structure to mitigate solder bridge risk Aug 25, 2021 Issued
Array ( [id] => 17448273 [patent_doc_number] => 20220068778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUSES AND SYSTEMS HAVING BALL GRID ARRAYS AND ASSOCIATED MICROELECTRONIC DEVICES AND DEVICE PACKAGES [patent_app_type] => utility [patent_app_number] => 17/411879 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411879
Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages Aug 24, 2021 Issued
Array ( [id] => 19376702 [patent_doc_number] => 12068282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Hybrid metallic structures in stacked semiconductor devices and associated systems and methods [patent_app_type] => utility [patent_app_number] => 17/405673 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6469 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405673
Hybrid metallic structures in stacked semiconductor devices and associated systems and methods Aug 17, 2021 Issued
Array ( [id] => 17870826 [patent_doc_number] => 20220293563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/405130 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405130
Semiconductor package including mold layer and manufacturing method thereof Aug 17, 2021 Issued
Array ( [id] => 17417148 [patent_doc_number] => 20220052052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/404056 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404056
Semiconductor structure and method for manufacturing semiconductor structure Aug 16, 2021 Issued
Array ( [id] => 18641243 [patent_doc_number] => 11765886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/397957 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397957
Semiconductor memory device Aug 8, 2021 Issued
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