Search

Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18061848 [patent_doc_number] => 20220392935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => IMAGE SENSOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/397106 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397106
IMAGE SENSOR AND MANUFACTURING METHOD THEREOF Aug 8, 2021 Abandoned
Array ( [id] => 18263112 [patent_doc_number] => 11610821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Method for forming a semiconductor device involving the use of stressor layer [patent_app_type] => utility [patent_app_number] => 17/381164 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1860 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381164
Method for forming a semiconductor device involving the use of stressor layer Jul 19, 2021 Issued
Array ( [id] => 18146010 [patent_doc_number] => 20230019866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/599532 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17599532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/599532
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL Jul 18, 2021 Pending
Array ( [id] => 17203625 [patent_doc_number] => 20210343720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/371061 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371061
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME Jul 7, 2021 Abandoned
Array ( [id] => 19031257 [patent_doc_number] => 11930632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Gate structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/594491 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4738 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/594491
Gate structure and manufacturing method thereof Jun 28, 2021 Issued
Array ( [id] => 19237503 [patent_doc_number] => 20240194698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE [patent_app_type] => utility [patent_app_number] => 17/772395 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17772395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/772395
Displaying base plate and manufacturing method thereof, and displaying device Jun 28, 2021 Issued
Array ( [id] => 18623871 [patent_doc_number] => 11756927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/357851 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357851
Semiconductor package structure Jun 23, 2021 Issued
Array ( [id] => 18593489 [patent_doc_number] => 11742401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor devices having an insulation layer in a recess and an impurity barrier layer extending along the insulation layer [patent_app_type] => utility [patent_app_number] => 17/340667 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 13237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340667
Semiconductor devices having an insulation layer in a recess and an impurity barrier layer extending along the insulation layer Jun 6, 2021 Issued
Array ( [id] => 17645269 [patent_doc_number] => 20220173008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING HIGH THERMAL CONDUCTIVITY LAYER [patent_app_type] => utility [patent_app_number] => 17/332471 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332471
Semiconductor package including high thermal conductivity layer May 26, 2021 Issued
Array ( [id] => 17566648 [patent_doc_number] => 20220130797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/332315 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332315
Semiconductor package May 26, 2021 Issued
Array ( [id] => 18827692 [patent_doc_number] => 11842982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Semiconductor package with curing layer between semiconductor chips [patent_app_type] => utility [patent_app_number] => 17/329230 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7715 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329230
Semiconductor package with curing layer between semiconductor chips May 24, 2021 Issued
Array ( [id] => 18488490 [patent_doc_number] => 20230215838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => Joining and Insulating Power Electronic Semiconductor Components [patent_app_type] => utility [patent_app_number] => 17/928318 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17928318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/928318
Joining and Insulating Power Electronic Semiconductor Components May 18, 2021 Pending
Array ( [id] => 18024397 [patent_doc_number] => 20220375896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Substrate Component Layout and Bonding Method for Increased Package Capacity [patent_app_type] => utility [patent_app_number] => 17/323132 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323132
Substrate component layout and bonding method for increased package capacity May 17, 2021 Issued
Array ( [id] => 18562992 [patent_doc_number] => 11728245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and semiconductor package including penetration via structure [patent_app_type] => utility [patent_app_number] => 17/316970 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 14081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316970
Semiconductor device and semiconductor package including penetration via structure May 10, 2021 Issued
Array ( [id] => 17431764 [patent_doc_number] => 20220059473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => PACKAGED SEMICONDUCTOR DEVICES HAVING SPACER CHIPS WITH PROTECTIVE GROOVE PATTERNS THEREIN [patent_app_type] => utility [patent_app_number] => 17/307266 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307266
Packaged semiconductor devices having spacer chips with protective groove patterns therein May 3, 2021 Issued
Array ( [id] => 18783835 [patent_doc_number] => 11825641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Pattern layout and the forming method thereof [patent_app_type] => utility [patent_app_number] => 17/306963 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4952 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306963
Pattern layout and the forming method thereof May 3, 2021 Issued
Array ( [id] => 17676691 [patent_doc_number] => 20220189858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SEMICONDUCTOR DEVICE PACKAGES INCLUDING MULTIPLE LEAD FRAMES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/301864 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301864
SEMICONDUCTOR DEVICE PACKAGES INCLUDING MULTIPLE LEAD FRAMES AND RELATED METHODS Apr 15, 2021 Pending
Array ( [id] => 18456429 [patent_doc_number] => 20230197711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => AI CHIP [patent_app_type] => utility [patent_app_number] => 17/995972 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17995972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/995972
AI CHIP Apr 13, 2021 Abandoned
Array ( [id] => 17389476 [patent_doc_number] => 20220037328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/210931 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210931
Semiconductor devices including a buried gate electrode Mar 23, 2021 Issued
Array ( [id] => 17901156 [patent_doc_number] => 20220310818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP [patent_app_type] => utility [patent_app_number] => 17/211751 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211751
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP Mar 23, 2021 Pending
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