Search

Kevin M. Johnson

Examiner (ID: 13728)

Most Active Art Unit
1793
Art Unit(s)
1732, 1793
Total Applications
255
Issued Applications
85
Pending Applications
85
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17417101 [patent_doc_number] => 20220052005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => INTERCONNECT STRUCTURE AND SEMICONDUCTOR CHIP INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/199674 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199674
Interconnect structure and semiconductor chip including the same Mar 11, 2021 Issued
Array ( [id] => 18464392 [patent_doc_number] => 11688687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor devices having landing pad patterns and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/198591 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 47 [patent_no_of_words] => 11988 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198591 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198591
Semiconductor devices having landing pad patterns and methods of manufacturing the same Mar 10, 2021 Issued
Array ( [id] => 17870785 [patent_doc_number] => 20220293522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Buried Power Rail Architecture [patent_app_type] => utility [patent_app_number] => 17/199143 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199143
Buried Power Rail Architecture Mar 10, 2021 Pending
Array ( [id] => 18563058 [patent_doc_number] => 11728311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor devices including interposer substrates further including capacitors [patent_app_type] => utility [patent_app_number] => 17/187985 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187985
Semiconductor devices including interposer substrates further including capacitors Feb 28, 2021 Issued
Array ( [id] => 18387338 [patent_doc_number] => 11658131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Semiconductor package with dummy pattern not electrically connected to circuit pattern [patent_app_type] => utility [patent_app_number] => 17/168337 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9978 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168337 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168337
Semiconductor package with dummy pattern not electrically connected to circuit pattern Feb 4, 2021 Issued
Array ( [id] => 18464391 [patent_doc_number] => 11688686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor device including an input/output circuit [patent_app_type] => utility [patent_app_number] => 17/163869 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 17369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163869
Semiconductor device including an input/output circuit Jan 31, 2021 Issued
Array ( [id] => 16995464 [patent_doc_number] => 20210233884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD [patent_app_type] => utility [patent_app_number] => 17/158781 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158781
Method of manufacturing semiconductor products, semiconductor product, device and testing method Jan 25, 2021 Issued
Array ( [id] => 17389402 [patent_doc_number] => 20220037254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/153220 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153220
SEMICONDUCTOR DEVICE INCLUDING POWER RAIL Jan 19, 2021 Pending
Array ( [id] => 17509090 [patent_doc_number] => 20220102193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/152390 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152390
Semiconductor device including semiconductor liner and method for fabricating the same Jan 18, 2021 Issued
Array ( [id] => 18688344 [patent_doc_number] => 11784087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor structure having layers in a trench and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/140627 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4934 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140627
Semiconductor structure having layers in a trench and method of manufacturing the same Jan 3, 2021 Issued
Array ( [id] => 17933326 [patent_doc_number] => 20220328452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR DEVICE FOR INTEGRATING POWER GATE CIRCUIT USING SILICON CONNECTION LAYER [patent_app_type] => utility [patent_app_number] => 17/311943 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311943
SEMICONDUCTOR DEVICE FOR INTEGRATING POWER GATE CIRCUIT USING SILICON CONNECTION LAYER Dec 29, 2020 Abandoned
Array ( [id] => 19063208 [patent_doc_number] => 11942460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Systems and methods for reducing the size of a semiconductor assembly [patent_app_type] => utility [patent_app_number] => 17/137085 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4919 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137085
Systems and methods for reducing the size of a semiconductor assembly Dec 28, 2020 Issued
Array ( [id] => 16780690 [patent_doc_number] => 20210117769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MONOLITHIC MULTI-BIT WEIGHT CELL FOR NEUROMORPHIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/133427 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133427
Monolithic multi-bit weight cell for neuromorphic computing Dec 22, 2020 Issued
Array ( [id] => 17676776 [patent_doc_number] => 20220189943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => LAYOUT FOR MEASURING OVERLAPPING STATE [patent_app_type] => utility [patent_app_number] => 17/124390 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124390
Layout for measuring overlapping state Dec 15, 2020 Issued
Array ( [id] => 17055874 [patent_doc_number] => 20210265308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => HIGH CAPACITY MEMORY MODULE INCLUDING WAFER-SECTION MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/124194 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124194
High capacity memory module including wafer-section memory circuit Dec 15, 2020 Issued
Array ( [id] => 18304450 [patent_doc_number] => 11626364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Fan-out semiconductor package and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/113284 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 99 [patent_no_of_words] => 20710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113284
Fan-out semiconductor package and electronic device including the same Dec 6, 2020 Issued
Array ( [id] => 18105527 [patent_doc_number] => 11545424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/952084 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8396 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952084
Package structure and manufacturing method thereof Nov 18, 2020 Issued
Array ( [id] => 16904864 [patent_doc_number] => 20210183780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/096107 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096107
Semiconductor packages including at least one supporting portion Nov 11, 2020 Issued
Array ( [id] => 20080922 [patent_doc_number] => 12355000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Package comprising a substrate and a high-density interconnect integrated device [patent_app_type] => utility [patent_app_number] => 17/094303 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 11512 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094303
Package comprising a substrate and a high-density interconnect integrated device Nov 9, 2020 Issued
Array ( [id] => 17862815 [patent_doc_number] => 11443976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Trench isolation process [patent_app_type] => utility [patent_app_number] => 16/949214 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949214
Trench isolation process Oct 19, 2020 Issued
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