
Kevin M Picardat
Examiner (ID: 16040, Phone: (571)272-1841 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 1104, 2822, 2813, 2825, 2899, 1763, 1732 |
| Total Applications | 2640 |
| Issued Applications | 2462 |
| Pending Applications | 47 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10022280
[patent_doc_number] => 09064775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Gallium nitride semiconductor structures with compositionally-graded transition layer'
[patent_app_type] => utility
[patent_app_number] => 14/452203
[patent_app_country] => US
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Array
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[patent_issue_date] => 2015-02-05
[patent_title] => 'LOCAL SEAL FOR ENCAPSULATION OF ELECTRO-OPTICAL ELEMENT ON A FLEXIBLE SUBSTRATE'
[patent_app_type] => utility
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Array
(
[id] => 10938482
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[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 14/446744
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Array
(
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[patent_issue_date] => 2015-08-20
[patent_title] => 'LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/330086
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/330086 | Low temperature spacer for advanced semiconductor devices | Jul 13, 2014 | Issued |
Array
(
[id] => 10502733
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[patent_title] => 'Method for preparing perovskite film and solar cell thereof'
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Array
(
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[patent_title] => 'HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/330158 | Heterogeneous source drain region and extension region | Jul 13, 2014 | Issued |
Array
(
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[patent_title] => 'Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/330063 | Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme | Jul 13, 2014 | Issued |
Array
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[id] => 11194277
[patent_doc_number] => 09425096
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[patent_issue_date] => 2016-08-23
[patent_title] => 'Air gap between tungsten metal lines for interconnects with reduced RC delay'
[patent_app_type] => utility
[patent_app_number] => 14/330950
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Array
(
[id] => 10460027
[patent_doc_number] => 20150345042
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[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'METHOD OF MANUFACTURING MICROSTRUCTURES OF METAL LINES'
[patent_app_type] => utility
[patent_app_number] => 14/329009
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/329009 | METHOD OF MANUFACTURING MICROSTRUCTURES OF METAL LINES | Jul 10, 2014 | Abandoned |
Array
(
[id] => 10667165
[patent_doc_number] => 20160013310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-14
[patent_title] => 'NON-VOLATILE FLOATING GATE MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 14/328938
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[patent_app_date] => 2014-07-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/328938 | Non-volatile floating gate memory cells | Jul 10, 2014 | Issued |
Array
(
[id] => 10138600
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[patent_title] => 'Combination finFET/ultra-thin body transistor structure and methods of making such structures'
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Array
(
[id] => 10165466
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Array
(
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Array
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[patent_title] => 'STRUCTURE AND METHOD FOR PROTECTING STRESS-SENSITIVE INTEGRATED CIRCUIT'
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Array
(
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Array
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[patent_title] => 'Self-Aligned Double Patterning'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/326562 | Method to improve memory cell erasure | Jul 8, 2014 | Issued |