Search

Kevin M Picardat

Examiner (ID: 16040, Phone: (571)272-1841 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
1104, 2822, 2813, 2825, 2899, 1763, 1732
Total Applications
2640
Issued Applications
2462
Pending Applications
47
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10022280 [patent_doc_number] => 09064775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Gallium nitride semiconductor structures with compositionally-graded transition layer' [patent_app_type] => utility [patent_app_number] => 14/452203 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452203
Gallium nitride semiconductor structures with compositionally-graded transition layer Aug 4, 2014 Issued
Array ( [id] => 9857900 [patent_doc_number] => 20150037916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'LOCAL SEAL FOR ENCAPSULATION OF ELECTRO-OPTICAL ELEMENT ON A FLEXIBLE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/452389 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 14032 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452389 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452389
Local seal for encapsulation of electro-optical element on a flexible substrate Aug 4, 2014 Issued
Array ( [id] => 10938482 [patent_doc_number] => 20140341503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/446744 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2251 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446744
Semiconductor substrate for photonic and electronic structures and method of manufacture Jul 29, 2014 Issued
Array ( [id] => 10351110 [patent_doc_number] => 20150236115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/330086 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4772 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330086
Low temperature spacer for advanced semiconductor devices Jul 13, 2014 Issued
Array ( [id] => 10502733 [patent_doc_number] => 09231136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Method for preparing perovskite film and solar cell thereof' [patent_app_type] => utility [patent_app_number] => 14/330521 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3952 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330521
Method for preparing perovskite film and solar cell thereof Jul 13, 2014 Issued
Array ( [id] => 10667168 [patent_doc_number] => 20160013313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION' [patent_app_type] => utility [patent_app_number] => 14/330158 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330158
Heterogeneous source drain region and extension region Jul 13, 2014 Issued
Array ( [id] => 10125264 [patent_doc_number] => 09159630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme' [patent_app_type] => utility [patent_app_number] => 14/330063 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330063
Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme Jul 13, 2014 Issued
Array ( [id] => 11194277 [patent_doc_number] => 09425096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Air gap between tungsten metal lines for interconnects with reduced RC delay' [patent_app_type] => utility [patent_app_number] => 14/330950 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6266 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330950 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330950
Air gap between tungsten metal lines for interconnects with reduced RC delay Jul 13, 2014 Issued
Array ( [id] => 10460027 [patent_doc_number] => 20150345042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHOD OF MANUFACTURING MICROSTRUCTURES OF METAL LINES' [patent_app_type] => utility [patent_app_number] => 14/329009 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5852 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329009
METHOD OF MANUFACTURING MICROSTRUCTURES OF METAL LINES Jul 10, 2014 Abandoned
Array ( [id] => 10667165 [patent_doc_number] => 20160013310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'NON-VOLATILE FLOATING GATE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/328938 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2745 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328938
Non-volatile floating gate memory cells Jul 10, 2014 Issued
Array ( [id] => 10138600 [patent_doc_number] => 09171922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-27 [patent_title] => 'Combination finFET/ultra-thin body transistor structure and methods of making such structures' [patent_app_type] => utility [patent_app_number] => 14/329263 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 5210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329263
Combination finFET/ultra-thin body transistor structure and methods of making such structures Jul 10, 2014 Issued
Array ( [id] => 10165466 [patent_doc_number] => 09196699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-24 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/328720 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2419 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328720
Semiconductor device and method for fabricating the same Jul 10, 2014 Issued
Array ( [id] => 11776126 [patent_doc_number] => 09385077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Integrated device comprising coaxial interconnect' [patent_app_type] => utility [patent_app_number] => 14/329646 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9518 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329646
Integrated device comprising coaxial interconnect Jul 10, 2014 Issued
Array ( [id] => 10666991 [patent_doc_number] => 20160013136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'STRUCTURE AND METHOD FOR PROTECTING STRESS-SENSITIVE INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/329883 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329883 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329883
STRUCTURE AND METHOD FOR PROTECTING STRESS-SENSITIVE INTEGRATED CIRCUIT Jul 10, 2014 Abandoned
Array ( [id] => 10079841 [patent_doc_number] => 09117695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-25 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/328697 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1807 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328697
Method for fabricating semiconductor device Jul 9, 2014 Issued
Array ( [id] => 10666958 [patent_doc_number] => 20160013103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Self-Aligned Double Patterning' [patent_app_type] => utility [patent_app_number] => 14/328174 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328174
Self-aligned double patterning Jul 9, 2014 Issued
Array ( [id] => 10132168 [patent_doc_number] => 09166011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Semiconductor device having stable gate structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/328247 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 4452 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328247
Semiconductor device having stable gate structure and method of manufacturing the same Jul 9, 2014 Issued
Array ( [id] => 10667163 [patent_doc_number] => 20160013308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'FINFET DEVICE WITH GATE OXIDE LAYER' [patent_app_type] => utility [patent_app_number] => 14/328350 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14328350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/328350
FinFET device with gate oxide layer Jul 9, 2014 Issued
Array ( [id] => 10028843 [patent_doc_number] => 09070753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'Method for fabricating memory device' [patent_app_type] => utility [patent_app_number] => 14/327255 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 4558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327255
Method for fabricating memory device Jul 8, 2014 Issued
Array ( [id] => 10667050 [patent_doc_number] => 20160013195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'METHOD TO IMPROVE MEMORY CELL ERASURE' [patent_app_type] => utility [patent_app_number] => 14/326562 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326562
Method to improve memory cell erasure Jul 8, 2014 Issued
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