Search

Kevin M. Picardat

Examiner (ID: 12154, Phone: (571)272-1841 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2825, 1763, 1732, 2822, 2813, 2899, 1104
Total Applications
2640
Issued Applications
2463
Pending Applications
47
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10022312 [patent_doc_number] => 09064806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Soft and conditionable chemical mechanical polishing pad with window' [patent_app_type] => utility [patent_app_number] => 14/228744 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14388 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228744
Soft and conditionable chemical mechanical polishing pad with window Mar 27, 2014 Issued
Array ( [id] => 10395024 [patent_doc_number] => 20150280031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SOLAR CELLS WITH TUNNEL DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 14/229769 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229769
Solar cells with tunnel dielectrics Mar 27, 2014 Issued
Array ( [id] => 10394737 [patent_doc_number] => 20150279744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'ANNEALING OXIDE GATE DIELECTRIC LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/228840 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228840
Annealing oxide gate dielectric layers for replacement metal gate field effect transistors Mar 27, 2014 Issued
Array ( [id] => 10394722 [patent_doc_number] => 20150279729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Semiconductor Structure With Anti-Etch Structure In Via And Method For Manufacturing The Same' [patent_app_type] => utility [patent_app_number] => 14/229264 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229264
Semiconductor structure with anti-etch structure in via and method for manufacturing the same Mar 27, 2014 Issued
Array ( [id] => 10389506 [patent_doc_number] => 20150274513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 14/226897 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226897
Semiconductor arrangement with thermal insulation configuration Mar 26, 2014 Issued
Array ( [id] => 10394726 [patent_doc_number] => 20150279733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'HARDMASK REMOVAL FOR COPPER INTERCONNECTS WITH TUNGSTEN CONTACTS BY CHEMICAL MECHANICAL POLISHING' [patent_app_type] => utility [patent_app_number] => 14/226891 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226891
Hardmask removal for copper interconnects with tungsten contacts by chemical mechanical polishing Mar 26, 2014 Issued
Array ( [id] => 11796684 [patent_doc_number] => 09406530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping' [patent_app_type] => utility [patent_app_number] => 14/227250 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 6668 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/227250
Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping Mar 26, 2014 Issued
Array ( [id] => 10066880 [patent_doc_number] => 09105742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-11 [patent_title] => 'Dual epitaxial process including spacer adjustment' [patent_app_type] => utility [patent_app_number] => 14/227267 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3893 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227267 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/227267
Dual epitaxial process including spacer adjustment Mar 26, 2014 Issued
Array ( [id] => 9615946 [patent_doc_number] => 20140205803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'METHOD FOR FORMING IDENTIFICATION MARKS ON SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE, AND SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/226910 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8204 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226910
Method for forming identification marks on silicon carbide single crystal substrate, and silicon carbide single crystal substrate Mar 26, 2014 Issued
Array ( [id] => 10394733 [patent_doc_number] => 20150279740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Kerf Preparation for Backside Metallization' [patent_app_type] => utility [patent_app_number] => 14/226666 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226666 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226666
Kerf preparation for backside metallization Mar 25, 2014 Issued
Array ( [id] => 10394956 [patent_doc_number] => 20150279963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE SO AS TO REDUCE PUNCH-THROUGH LEAKAGE CURRENTS AND THE RESULTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/226488 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7262 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226488
Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device Mar 25, 2014 Issued
Array ( [id] => 10125443 [patent_doc_number] => 09159812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Fin sidewall removal to enlarge epitaxial source/drain volume' [patent_app_type] => utility [patent_app_number] => 14/225912 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/225912
Fin sidewall removal to enlarge epitaxial source/drain volume Mar 25, 2014 Issued
Array ( [id] => 10028854 [patent_doc_number] => 09070763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'Semiconductor device layout structure' [patent_app_type] => utility [patent_app_number] => 14/225932 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6138 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/225932
Semiconductor device layout structure Mar 25, 2014 Issued
Array ( [id] => 10706991 [patent_doc_number] => 20160053137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'PRODUCTION METHOD FOR LAMINATE FILM, LAMINATE FILM, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE EMPLOYING SAME' [patent_app_type] => utility [patent_app_number] => 14/780092 [patent_app_country] => US [patent_app_date] => 2014-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14780092 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/780092
Production method for laminate film, laminate film, and production method for semiconductor device employing same Mar 24, 2014 Issued
Array ( [id] => 9594725 [patent_doc_number] => 20140191402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'Barrier Layer for Copper Interconnect' [patent_app_type] => utility [patent_app_number] => 14/204347 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3759 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/204347
Barrier layer for copper interconnect Mar 10, 2014 Issued
Array ( [id] => 10093199 [patent_doc_number] => 09130030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Baking tool for improved wafer coating process' [patent_app_type] => utility [patent_app_number] => 14/200918 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200918 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200918
Baking tool for improved wafer coating process Mar 6, 2014 Issued
Array ( [id] => 10892819 [patent_doc_number] => 08916431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Semiconductor device having epitaxial semiconductor layer above impurity layer' [patent_app_type] => utility [patent_app_number] => 14/188132 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 51 [patent_no_of_words] => 10381 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188132
Semiconductor device having epitaxial semiconductor layer above impurity layer Feb 23, 2014 Issued
Array ( [id] => 9922743 [patent_doc_number] => 08980702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Method of making a transistor' [patent_app_type] => utility [patent_app_number] => 14/177614 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 14917 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177614 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177614
Method of making a transistor Feb 10, 2014 Issued
Array ( [id] => 9875132 [patent_doc_number] => 08962399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Method of making a semiconductor layer having at least two different thicknesses' [patent_app_type] => utility [patent_app_number] => 14/177593 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 6916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177593 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177593
Method of making a semiconductor layer having at least two different thicknesses Feb 10, 2014 Issued
Array ( [id] => 11257035 [patent_doc_number] => 09481929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Vapor deposition apparatus, vapor deposition method and method of manufacturing organic light emitting display apparatus' [patent_app_type] => utility [patent_app_number] => 14/177180 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8146 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177180 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177180
Vapor deposition apparatus, vapor deposition method and method of manufacturing organic light emitting display apparatus Feb 9, 2014 Issued
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