Search

Kevin M. Picardat

Examiner (ID: 9381, Phone: (571)272-1841 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2813, 2825, 1104, 2899, 2822, 1763, 1732
Total Applications
2640
Issued Applications
2463
Pending Applications
47
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11453524 [patent_doc_number] => 09577179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Electrostatically controlled magnetic logic device' [patent_app_type] => utility [patent_app_number] => 13/761792 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3202 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761792
Electrostatically controlled magnetic logic device Feb 6, 2013 Issued
Array ( [id] => 9099526 [patent_doc_number] => 08563400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Laser bonding for stacking semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 13/758745 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758745 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758745
Laser bonding for stacking semiconductor substrates Feb 3, 2013 Issued
Array ( [id] => 9144312 [patent_doc_number] => 20130298835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MULTIPLE PRECURSOR SHOWERHEAD WITH BY-PASS PORTS' [patent_app_type] => utility [patent_app_number] => 13/751889 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6479 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/751889
Multiple precursor showerhead with by-pass ports Jan 27, 2013 Issued
Array ( [id] => 9569298 [patent_doc_number] => 20140187011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Methods for Forming FinFETs with Self-Aligned Source/Drain' [patent_app_type] => utility [patent_app_number] => 13/728837 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728837
Methods for forming FinFETs with self-aligned source/drain Dec 26, 2012 Issued
Array ( [id] => 9311713 [patent_doc_number] => 08652931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'Method of dual-depth STI formation' [patent_app_type] => utility [patent_app_number] => 13/728190 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4048 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728190 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728190
Method of dual-depth STI formation Dec 26, 2012 Issued
Array ( [id] => 9167178 [patent_doc_number] => 08592862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Gallium nitride semiconductor structures with compositionally-graded transition layer' [patent_app_type] => utility [patent_app_number] => 13/728956 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728956
Gallium nitride semiconductor structures with compositionally-graded transition layer Dec 26, 2012 Issued
Array ( [id] => 9561320 [patent_doc_number] => 20140179033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Methods for Forming Templated Materials' [patent_app_type] => utility [patent_app_number] => 13/727237 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727237 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727237
Methods for forming templated materials Dec 25, 2012 Issued
Array ( [id] => 10844479 [patent_doc_number] => 08871655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Method of forming silicon oxycarbonitride film' [patent_app_type] => utility [patent_app_number] => 13/726778 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 8210 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726778 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726778
Method of forming silicon oxycarbonitride film Dec 25, 2012 Issued
Array ( [id] => 9311716 [patent_doc_number] => 08652934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'Semiconductor substrate for photonic and electronic structures and method of manufacture' [patent_app_type] => utility [patent_app_number] => 13/726891 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2203 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726891
Semiconductor substrate for photonic and electronic structures and method of manufacture Dec 25, 2012 Issued
Array ( [id] => 8792169 [patent_doc_number] => 20130109138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/726326 [patent_app_country] => US [patent_app_date] => 2012-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726326
Manufacturing method of semiconductor device Dec 23, 2012 Issued
Array ( [id] => 8989961 [patent_doc_number] => 20130217242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Program' [patent_app_type] => utility [patent_app_number] => 13/725953 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725953
Substrate processing apparatus, method of manufacturing semiconductor device and program Dec 20, 2012 Issued
Array ( [id] => 9174554 [patent_doc_number] => 20130316539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UNDOPED POLYSILICON GATES AFTER ETCHING' [patent_app_type] => utility [patent_app_number] => 13/721073 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2394 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721073
Method for reducing morphological difference between N-doped and undoped polysilicon gates after etching Dec 19, 2012 Issued
Array ( [id] => 9662180 [patent_doc_number] => 08809154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/721972 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 23514 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721972
Semiconductor device and method for manufacturing the same Dec 19, 2012 Issued
Array ( [id] => 9455097 [patent_doc_number] => 08716104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Method of fabricating isolation structure' [patent_app_type] => utility [patent_app_number] => 13/721021 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2782 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721021
Method of fabricating isolation structure Dec 19, 2012 Issued
Array ( [id] => 9311644 [patent_doc_number] => 08652861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'HPC optimization of contacts to optoelectronic devices' [patent_app_type] => utility [patent_app_number] => 13/722744 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8662 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722744
HPC optimization of contacts to optoelectronic devices Dec 19, 2012 Issued
Array ( [id] => 9561410 [patent_doc_number] => 20140179123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Site-Isolated Rapid Thermal Processing Methods and Apparatus' [patent_app_type] => utility [patent_app_number] => 13/722624 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7255 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722624
Site-isolated rapid thermal processing methods and apparatus Dec 19, 2012 Issued
Array ( [id] => 9323491 [patent_doc_number] => 08658511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Etching resistive switching and electrode layers' [patent_app_type] => utility [patent_app_number] => 13/722714 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722714 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722714
Etching resistive switching and electrode layers Dec 19, 2012 Issued
Array ( [id] => 9323511 [patent_doc_number] => 08658531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Method of forming connection holes' [patent_app_type] => utility [patent_app_number] => 13/721070 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721070
Method of forming connection holes Dec 19, 2012 Issued
Array ( [id] => 9323419 [patent_doc_number] => 08658438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Measurement of lateral diffusion of implanted ions in doped well region of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/721082 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721082 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721082
Measurement of lateral diffusion of implanted ions in doped well region of semiconductor devices Dec 19, 2012 Issued
Array ( [id] => 9561317 [patent_doc_number] => 20140179030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Dissolution Rate Monitor' [patent_app_type] => utility [patent_app_number] => 13/721534 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721534 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721534
Dissolution rate monitor Dec 19, 2012 Issued
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