Search

Kevin V. Quinto

Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2817, 2821, 2829, 2893
Total Applications
1390
Issued Applications
1170
Pending Applications
65
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16425081 [patent_doc_number] => 20200350279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => Integrated Fan-Out Package Structures with Recesses in Molding Compound [patent_app_type] => utility [patent_app_number] => 16/933593 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933593
Integrated fan-out package structures with recesses in molding compound Jul 19, 2020 Issued
Array ( [id] => 19509440 [patent_doc_number] => 12120881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Three-dimensional semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/931500 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931500
Three-dimensional semiconductor devices Jul 16, 2020 Issued
Array ( [id] => 18623827 [patent_doc_number] => 11756883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Through via structure and method [patent_app_type] => utility [patent_app_number] => 16/927249 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927249
Through via structure and method Jul 12, 2020 Issued
Array ( [id] => 17623265 [patent_doc_number] => 11342329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Semiconductor memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/903586 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 8758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903586
Semiconductor memory device and method of fabricating the same Jun 16, 2020 Issued
Array ( [id] => 17623270 [patent_doc_number] => 11342334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Memory cell and method [patent_app_type] => utility [patent_app_number] => 16/901885 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 55 [patent_no_of_words] => 8940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901885
Memory cell and method Jun 14, 2020 Issued
Array ( [id] => 17055930 [patent_doc_number] => 20210265364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/892439 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/892439
Memory device and method for forming the same Jun 3, 2020 Issued
Array ( [id] => 17262910 [patent_doc_number] => 20210375895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/889726 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889726
Semiconductor non-volatile memory devices May 31, 2020 Issued
Array ( [id] => 17032881 [patent_doc_number] => 11094699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Apparatuses including stacked horizontal capacitor structures and related methods, memory devices, and electronic systems [patent_app_type] => utility [patent_app_number] => 16/886497 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 14962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886497
Apparatuses including stacked horizontal capacitor structures and related methods, memory devices, and electronic systems May 27, 2020 Issued
Array ( [id] => 16286346 [patent_doc_number] => 20200279948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => POWER MOSFETS STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/878229 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878229 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878229
Power MOSFETs structure May 18, 2020 Issued
Array ( [id] => 17152568 [patent_doc_number] => 11145659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/876142 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876142
Semiconductor structure and method of forming the same May 17, 2020 Issued
Array ( [id] => 16286153 [patent_doc_number] => 20200279755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/877116 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877116
Semiconductor device and method May 17, 2020 Issued
Array ( [id] => 16272495 [patent_doc_number] => 20200273983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/930784 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930784 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930784
Semiconductor device, and method for manufacturing the same May 12, 2020 Issued
Array ( [id] => 17530011 [patent_doc_number] => 11302712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells [patent_app_type] => utility [patent_app_number] => 16/856847 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 37 [patent_no_of_words] => 7841 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856847
Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells Apr 22, 2020 Issued
Array ( [id] => 18131374 [patent_doc_number] => 11557591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Transistors, memory arrays, and methods used in forming an array of memory cells individually comprising a transistor [patent_app_type] => utility [patent_app_number] => 16/855446 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 50 [patent_no_of_words] => 5894 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855446
Transistors, memory arrays, and methods used in forming an array of memory cells individually comprising a transistor Apr 21, 2020 Issued
Array ( [id] => 17122113 [patent_doc_number] => 11133255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Metal patterning for internal cell routing [patent_app_type] => utility [patent_app_number] => 16/852604 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/852604
Metal patterning for internal cell routing Apr 19, 2020 Issued
Array ( [id] => 16180588 [patent_doc_number] => 20200227557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/835661 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835661
SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME Mar 30, 2020 Abandoned
Array ( [id] => 17683470 [patent_doc_number] => 11367735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Three-dimensional semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/835484 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10813 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835484
Three-dimensional semiconductor devices Mar 30, 2020 Issued
Array ( [id] => 16180503 [patent_doc_number] => 20200227472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/831658 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831658 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831658
LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS Mar 25, 2020 Abandoned
Array ( [id] => 17529998 [patent_doc_number] => 11302698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Methods of forming a capacitor, semiconductor device, and fine pattern, and semiconductor device formed by the methods [patent_app_type] => utility [patent_app_number] => 16/829025 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 9490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829025
Methods of forming a capacitor, semiconductor device, and fine pattern, and semiconductor device formed by the methods Mar 24, 2020 Issued
Array ( [id] => 17130487 [patent_doc_number] => 20210305256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => DRAM WITH SELECTIVE EPITAXIAL TRANSISTOR AND BURIED BITLINE [patent_app_type] => utility [patent_app_number] => 16/828879 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828879
DRAM with selective epitaxial transistor and buried bitline Mar 23, 2020 Issued
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