Search

Kevin V. Quinto

Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2817, 2821, 2829, 2893
Total Applications
1390
Issued Applications
1170
Pending Applications
65
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14151725 [patent_doc_number] => 10256252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Three-dimensional memory device containing structurally reinforced pedestal channel portions and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/840090 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 17100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840090
Three-dimensional memory device containing structurally reinforced pedestal channel portions and methods of making the same Dec 12, 2017 Issued
Array ( [id] => 15108741 [patent_doc_number] => 10475701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Mixed wire structure and method of making the same [patent_app_type] => utility [patent_app_number] => 15/840002 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5220 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840002
Mixed wire structure and method of making the same Dec 12, 2017 Issued
Array ( [id] => 14859185 [patent_doc_number] => 10418327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/840257 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8394 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840257
Semiconductor device Dec 12, 2017 Issued
Array ( [id] => 14397829 [patent_doc_number] => 10312206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Array substrate [patent_app_type] => utility [patent_app_number] => 15/839870 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 20511 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839870
Array substrate Dec 12, 2017 Issued
Array ( [id] => 12849385 [patent_doc_number] => 20180174968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => Source-Gate Region Architecture in a Vertical Power Semiconductor Device [patent_app_type] => utility [patent_app_number] => 15/824792 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824792
Source-Gate Region Architecture in a Vertical Power Semiconductor Device Nov 27, 2017 Abandoned
Array ( [id] => 16239942 [patent_doc_number] => 20200257176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/777178 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15777178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/777178
ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE Nov 8, 2017 Abandoned
Array ( [id] => 12236256 [patent_doc_number] => 20180069119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/806535 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8139 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806535
SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME Nov 7, 2017 Abandoned
Array ( [id] => 12759562 [patent_doc_number] => 20180145022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Through Via Structure and Method [patent_app_type] => utility [patent_app_number] => 15/801681 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801681
Through via structure and method Nov 1, 2017 Issued
Array ( [id] => 17971323 [patent_doc_number] => 11488871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Transistor structure with multiple halo implants having epitaxial layer over semiconductor-on-insulator substrate [patent_app_type] => utility [patent_app_number] => 15/708973 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 11134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708973
Transistor structure with multiple halo implants having epitaxial layer over semiconductor-on-insulator substrate Sep 18, 2017 Issued
Array ( [id] => 15519481 [patent_doc_number] => 10566339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Semiconductor memory device and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/691931 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 71 [patent_no_of_words] => 13698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691931 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691931
Semiconductor memory device and method for manufacturing same Aug 30, 2017 Issued
Array ( [id] => 13514507 [patent_doc_number] => 20180308796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => Metal Patterning For Internal Cell Routing [patent_app_type] => utility [patent_app_number] => 15/691936 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691936
Metal patterning for internal cell routing Aug 30, 2017 Issued
Array ( [id] => 13996029 [patent_doc_number] => 20190067172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING [patent_app_type] => utility [patent_app_number] => 15/691797 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691797 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691797
Packaged semiconductor device and method for forming Aug 30, 2017 Issued
Array ( [id] => 14985267 [patent_doc_number] => 10446555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Buried metal track and methods forming same [patent_app_type] => utility [patent_app_number] => 15/691974 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 7102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691974
Buried metal track and methods forming same Aug 30, 2017 Issued
Array ( [id] => 13293333 [patent_doc_number] => 10157867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Interconnect structure and method [patent_app_type] => utility [patent_app_number] => 15/692067 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692067
Interconnect structure and method Aug 30, 2017 Issued
Array ( [id] => 13709195 [patent_doc_number] => 20170365552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/693083 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693083
Semiconductor device and a method for fabricating the same Aug 30, 2017 Issued
Array ( [id] => 12241228 [patent_doc_number] => 20180074091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'PIEZORESISTIVE SENSOR' [patent_app_type] => utility [patent_app_number] => 15/691790 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4813 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691790
PIEZORESISTIVE SENSOR Aug 30, 2017 Abandoned
Array ( [id] => 13995705 [patent_doc_number] => 20190067010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MULTIPLE PATTERNING WITH VARIABLE SPACE MANDREL CUTS [patent_app_type] => utility [patent_app_number] => 15/689668 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689668 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689668
Multiple patterning with variable space mandrel cuts Aug 28, 2017 Issued
Array ( [id] => 13214605 [patent_doc_number] => 10121678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/689964 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 10848 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689964 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689964
Method of manufacturing semiconductor device Aug 28, 2017 Issued
Array ( [id] => 17018332 [patent_doc_number] => 11087977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => P-type oxide semiconductor and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 16/326569 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10334 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326569 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/326569
P-type oxide semiconductor and method for manufacturing same Aug 28, 2017 Issued
Array ( [id] => 15315885 [patent_doc_number] => 10522660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Method for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/690260 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3167 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690260 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690260
Method for fabricating semiconductor device Aug 28, 2017 Issued
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