
Kevin V. Quinto
Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826, 2817, 2821, 2829, 2893 |
| Total Applications | 1390 |
| Issued Applications | 1170 |
| Pending Applications | 65 |
| Abandoned Applications | 180 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14676935
[patent_doc_number] => 20190237582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-01
[patent_title] => MAGNESIUM ZINC OXIDE-BASED HIGH VOLTAGE THIN FILM TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 16/326575
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326575
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/326575 | Magnesium zinc oxide-based high voltage thin film transistor | Aug 17, 2017 | Issued |
Array
(
[id] => 15401423
[patent_doc_number] => 10541375
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-21
[patent_title] => Display device and electronic device
[patent_app_type] => utility
[patent_app_number] => 15/654108
[patent_app_country] => US
[patent_app_date] => 2017-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 45
[patent_no_of_words] => 19392
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654108
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/654108 | Display device and electronic device | Jul 18, 2017 | Issued |
Array
(
[id] => 12596460
[patent_doc_number] => 20180090650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => LIGHT EMITTING DEVICE AND ELECTRONIC COMPONENT
[patent_app_type] => utility
[patent_app_number] => 15/648344
[patent_app_country] => US
[patent_app_date] => 2017-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7257
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648344
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648344 | Light emitting device and electronic component | Jul 11, 2017 | Issued |
Array
(
[id] => 12412128
[patent_doc_number] => 09970981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-15
[patent_title] => Method and device for temperature measurement of FinFET devices
[patent_app_type] => utility
[patent_app_number] => 15/648408
[patent_app_country] => US
[patent_app_date] => 2017-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3868
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648408
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648408 | Method and device for temperature measurement of FinFET devices | Jul 11, 2017 | Issued |
Array
(
[id] => 13257089
[patent_doc_number] => 10141238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-11-27
[patent_title] => Semiconductor power device including adjacent thermal substrate for thermal impedance reduction
[patent_app_type] => utility
[patent_app_number] => 15/648348
[patent_app_country] => US
[patent_app_date] => 2017-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 7578
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648348
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648348 | Semiconductor power device including adjacent thermal substrate for thermal impedance reduction | Jul 11, 2017 | Issued |
Array
(
[id] => 12141220
[patent_doc_number] => 20180019302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'SEMICONDUCTOR DEVICES WITH DEPLETED HETEROJUNCTION CURRENT BLOCKING REGIONS'
[patent_app_type] => utility
[patent_app_number] => 15/648235
[patent_app_country] => US
[patent_app_date] => 2017-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10450
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648235
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648235 | Semiconductor devices with depleted heterojunction current blocking regions | Jul 11, 2017 | Issued |
| 15/635524 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Snake Open Configured Fill Cells, and the Second DOE Including Stitch Open Configured Fill Cells | Jun 27, 2017 | Abandoned |
Array
(
[id] => 13976903
[patent_doc_number] => 10217820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 15/632884
[patent_app_country] => US
[patent_app_date] => 2017-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 7535
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632884
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/632884 | Semiconductor devices | Jun 25, 2017 | Issued |
Array
(
[id] => 11983945
[patent_doc_number] => 20170288100
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'PACKAGE METHOD AND PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 15/627430
[patent_app_country] => US
[patent_app_date] => 2017-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3594
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627430
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/627430 | Package method and package | Jun 18, 2017 | Issued |
Array
(
[id] => 12516423
[patent_doc_number] => 10002942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Semiconductor device and method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/602793
[patent_app_country] => US
[patent_app_date] => 2017-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 99
[patent_no_of_words] => 19573
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602793
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/602793 | Semiconductor device and method of manufacturing semiconductor device | May 22, 2017 | Issued |
Array
(
[id] => 16495948
[patent_doc_number] => 10862003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Component having enhanced efficiency and method for production thereof
[patent_app_type] => utility
[patent_app_number] => 16/303571
[patent_app_country] => US
[patent_app_date] => 2017-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7187
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303571
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/303571 | Component having enhanced efficiency and method for production thereof | May 17, 2017 | Issued |
Array
(
[id] => 12061931
[patent_doc_number] => 20170338275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'LIGHT EMITTING DIODES (LEDs) WITH STACKED MULTI-COLOR PIXELS FOR DISPLAYS'
[patent_app_type] => utility
[patent_app_number] => 15/599427
[patent_app_country] => US
[patent_app_date] => 2017-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 16302
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599427
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/599427 | Light emitting diodes (LEDs) with stacked multi-color pixels for displays | May 17, 2017 | Issued |
Array
(
[id] => 13565665
[patent_doc_number] => 20180334380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/599377
[patent_app_country] => US
[patent_app_date] => 2017-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599377
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/599377 | Semiconductor device package and a method of manufacturing the same | May 17, 2017 | Issued |
Array
(
[id] => 13695571
[patent_doc_number] => 20170358740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => Logic Chip Including Embedded Magnetic Tunnel Junctions
[patent_app_type] => utility
[patent_app_number] => 15/596650
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6497
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596650
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596650 | Logic chip including embedded magnetic tunnel junctions | May 15, 2017 | Issued |
Array
(
[id] => 13131883
[patent_doc_number] => 10083881
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Array substrate for display device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/592624
[patent_app_country] => US
[patent_app_date] => 2017-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 9931
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592624
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/592624 | Array substrate for display device and manufacturing method thereof | May 10, 2017 | Issued |
Array
(
[id] => 16566780
[patent_doc_number] => 10892156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-12
[patent_title] => Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
[patent_app_type] => utility
[patent_app_number] => 15/589861
[patent_app_country] => US
[patent_app_date] => 2017-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8422
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589861
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/589861 | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures | May 7, 2017 | Issued |
Array
(
[id] => 14617149
[patent_doc_number] => 10361282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-23
[patent_title] => Method for forming a low-K spacer
[patent_app_type] => utility
[patent_app_number] => 15/589659
[patent_app_country] => US
[patent_app_date] => 2017-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 8210
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589659
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/589659 | Method for forming a low-K spacer | May 7, 2017 | Issued |
Array
(
[id] => 14366833
[patent_doc_number] => 10304729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Method of forming interconnect structures
[patent_app_type] => utility
[patent_app_number] => 15/587140
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5817
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587140
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/587140 | Method of forming interconnect structures | May 3, 2017 | Issued |
Array
(
[id] => 13188003
[patent_doc_number] => 10109528
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-23
[patent_title] => Wafer processing method
[patent_app_type] => utility
[patent_app_number] => 15/586889
[patent_app_country] => US
[patent_app_date] => 2017-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 6242
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586889
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/586889 | Wafer processing method | May 3, 2017 | Issued |
Array
(
[id] => 12168322
[patent_doc_number] => 09887094
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-02-06
[patent_title] => 'Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device'
[patent_app_type] => utility
[patent_app_number] => 15/585800
[patent_app_country] => US
[patent_app_date] => 2017-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 5183
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585800
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/585800 | Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device | May 2, 2017 | Issued |