Search

Kevin V. Quinto

Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2817, 2821, 2829, 2893
Total Applications
1390
Issued Applications
1170
Pending Applications
65
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13543361 [patent_doc_number] => 20180323227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => WAFER LEVEL PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/586102 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586102
Wafer level packaging method May 2, 2017 Issued
Array ( [id] => 13030623 [patent_doc_number] => 10037935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => Lead frame with dummy leads for burr mitigation during encapsulation [patent_app_type] => utility [patent_app_number] => 15/499355 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499355
Lead frame with dummy leads for burr mitigation during encapsulation Apr 26, 2017 Issued
Array ( [id] => 12692965 [patent_doc_number] => 20180122821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/499291 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499291
Method of manufacturing semiconductor device Apr 26, 2017 Issued
Array ( [id] => 14429537 [patent_doc_number] => 10319582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Methods and apparatus for depositing silicon oxide on metal layers [patent_app_type] => utility [patent_app_number] => 15/499318 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9447 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499318
Methods and apparatus for depositing silicon oxide on metal layers Apr 26, 2017 Issued
Array ( [id] => 13257179 [patent_doc_number] => 10141286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Methods of manufacturing semiconductor packages [patent_app_type] => utility [patent_app_number] => 15/499229 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 7749 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499229
Methods of manufacturing semiconductor packages Apr 26, 2017 Issued
Array ( [id] => 13653555 [patent_doc_number] => 09853099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Double diffused metal oxide semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/490626 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7836 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 698 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490626
Double diffused metal oxide semiconductor device and manufacturing method thereof Apr 17, 2017 Issued
Array ( [id] => 12033849 [patent_doc_number] => 20170323948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'VERTICAL TRANSISTOR WITH A BODY CONTACT FOR BACK-BIASING' [patent_app_type] => utility [patent_app_number] => 15/483125 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483125
Vertical transistor with a body contact for back-biasing Apr 9, 2017 Issued
Array ( [id] => 11760163 [patent_doc_number] => 20170207033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'MAXIMIZING THE POWER CONVERSION EFFICIENCY OF A TIN PEROVSKITE/SILICON THIN-FILM TANDEM SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 15/479388 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7194 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479388
Maximizing the power conversion efficiency of a tin perovskite/silicon thin-film tandem solar cell Apr 4, 2017 Issued
Array ( [id] => 11990187 [patent_doc_number] => 20170294343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'ETCHING METHOD AND FABRICATION METHOD OF SEMICONDUCTOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/475413 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475413
Etching method and fabrication method of semiconductor structures Mar 30, 2017 Issued
Array ( [id] => 14191655 [patent_doc_number] => 20190115533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => METHOD FOR THE PRODUCTION OF LAYERS OF RERAM MEMORIES, AND USE OF AN IMPLANTATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/090594 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16090594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/090594
METHOD FOR THE PRODUCTION OF LAYERS OF RERAM MEMORIES, AND USE OF AN IMPLANTATION DEVICE Mar 30, 2017 Abandoned
Array ( [id] => 13145661 [patent_doc_number] => 10090169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-02 [patent_title] => Methods of forming integrated circuit structures including opening filled with insulator in metal gate [patent_app_type] => utility [patent_app_number] => 15/475272 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 4470 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475272
Methods of forming integrated circuit structures including opening filled with insulator in metal gate Mar 30, 2017 Issued
Array ( [id] => 16064067 [patent_doc_number] => 10690975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Active matrix substrate, manufacturing method therefor and display device [patent_app_type] => utility [patent_app_number] => 16/088851 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18835 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16088851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/088851
Active matrix substrate, manufacturing method therefor and display device Mar 23, 2017 Issued
Array ( [id] => 16316336 [patent_doc_number] => 20200295074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SOLID-STATE IMAGE SENSOR AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/086248 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/086248
Solid-state image sensor and electronic apparatus Mar 13, 2017 Issued
Array ( [id] => 15760751 [patent_doc_number] => 10622508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Method for manufacturing an optoelectronic component, and optoelectronic component [patent_app_type] => utility [patent_app_number] => 15/775817 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 5365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775817
Method for manufacturing an optoelectronic component, and optoelectronic component Feb 23, 2017 Issued
Array ( [id] => 11939704 [patent_doc_number] => 20170243854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'CIRCUIT SUBSTRATE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/436449 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6024 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436449
Circuit substrate and method of manufacturing same Feb 16, 2017 Issued
Array ( [id] => 11630850 [patent_doc_number] => 20170141038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 15/417940 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417940
Self-aligned contact process enabled by low temperature Jan 26, 2017 Issued
Array ( [id] => 12027213 [patent_doc_number] => 20170317312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'ORGANIC LIGHT EMITTING DEVICES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/417624 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417624
Organic light emitting devices and methods of fabricating the same Jan 26, 2017 Issued
Array ( [id] => 11983628 [patent_doc_number] => 20170287783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/416390 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6177 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/416390
Semiconductor device manufacturing method Jan 25, 2017 Issued
Array ( [id] => 13653167 [patent_doc_number] => 09852903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET [patent_app_type] => utility [patent_app_number] => 15/416287 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/416287
System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET Jan 25, 2017 Issued
Array ( [id] => 13187935 [patent_doc_number] => 10109494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => FinFet spacer etch with no fin recess and no gate-spacer pull-down [patent_app_type] => utility [patent_app_number] => 15/414883 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5812 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414883
FinFet spacer etch with no fin recess and no gate-spacer pull-down Jan 24, 2017 Issued
Menu