Search

Kevin V. Quinto

Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2817, 2821, 2829, 2893
Total Applications
1390
Issued Applications
1170
Pending Applications
65
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8333199 [patent_doc_number] => 20120199901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/366259 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9341 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366259
Semiconductor device Feb 2, 2012 Issued
Array ( [id] => 8960893 [patent_doc_number] => 20130200495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'BUFFER LAYER STRUCTURES SUITED FOR III-NITRIDE DEVICES WITH FOREIGN SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/366090 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8007 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366090
Buffer layer structures suited for III-nitride devices with foreign substrates Feb 2, 2012 Issued
Array ( [id] => 9938040 [patent_doc_number] => 08987852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Solid-state image pickup apparatus, image pickup system including solid-state image pickup apparatus, and method for manufacturing solid-state image pickup apparatus' [patent_app_type] => utility [patent_app_number] => 13/366189 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 15715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366189
Solid-state image pickup apparatus, image pickup system including solid-state image pickup apparatus, and method for manufacturing solid-state image pickup apparatus Feb 2, 2012 Issued
Array ( [id] => 8166172 [patent_doc_number] => 20120104461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods' [patent_app_type] => utility [patent_app_number] => 13/348778 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104461.pdf [firstpage_image] =>[orig_patent_app_number] => 13348778 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348778
Semiconductor heterostructures having reduced dislocation pile-ups and related methods Jan 11, 2012 Issued
Array ( [id] => 10195894 [patent_doc_number] => 09224810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'CMOS nanowire structure' [patent_app_type] => utility [patent_app_number] => 13/996503 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8525 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996503
CMOS nanowire structure Dec 22, 2011 Issued
Array ( [id] => 9631746 [patent_doc_number] => 20140209855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS' [patent_app_type] => utility [patent_app_number] => 13/995914 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6577 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995914 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995914
Nanowire structures having wrap-around contacts Dec 22, 2011 Issued
Array ( [id] => 10060080 [patent_doc_number] => 09099444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => '3D integrated circuit package with through-mold first level interconnects' [patent_app_type] => utility [patent_app_number] => 13/995778 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6326 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995778 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995778
3D integrated circuit package with through-mold first level interconnects Dec 21, 2011 Issued
Array ( [id] => 9113580 [patent_doc_number] => 08569757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Semiconductor device with amorphous silicon MAS memory cell structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/333994 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6855 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333994
Semiconductor device with amorphous silicon MAS memory cell structure and manufacturing method thereof Dec 20, 2011 Issued
Array ( [id] => 8133829 [patent_doc_number] => 20120091462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'TFT MONOS OR SONOS MEMORY CELL STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/332259 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6758 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20120091462.pdf [firstpage_image] =>[orig_patent_app_number] => 13332259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332259
TFT MONOS or SONOS memory cell structures Dec 19, 2011 Issued
Array ( [id] => 8205176 [patent_doc_number] => 20120126351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Interconnection system on a plane adjacent to a solid-state device structure' [patent_app_type] => utility [patent_app_number] => 13/311862 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5194 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126351.pdf [firstpage_image] =>[orig_patent_app_number] => 13311862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311862
Interconnection system on a plane adjacent to a solid-state device structure Dec 5, 2011 Abandoned
Array ( [id] => 9010052 [patent_doc_number] => 08525354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Bond pad structure and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 13/272289 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3248 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272289
Bond pad structure and fabricating method thereof Oct 12, 2011 Issued
Array ( [id] => 10138594 [patent_doc_number] => 09171916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-27 [patent_title] => 'LDMOS with thick interlayer-dielectric layer' [patent_app_type] => utility [patent_app_number] => 13/272301 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4971 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272301
LDMOS with thick interlayer-dielectric layer Oct 12, 2011 Issued
Array ( [id] => 8765047 [patent_doc_number] => 20130093084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Wafer-Level Chip Scale Package with Re-Workable Underfill' [patent_app_type] => utility [patent_app_number] => 13/272009 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272009 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272009
Wafer-level chip scale package with re-workable underfill Oct 11, 2011 Issued
Array ( [id] => 10851498 [patent_doc_number] => 08878182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Probe pad design for 3DIC package yield analysis' [patent_app_type] => utility [patent_app_number] => 13/272004 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2833 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272004 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272004
Probe pad design for 3DIC package yield analysis Oct 11, 2011 Issued
Array ( [id] => 8725998 [patent_doc_number] => 08405119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Organic light emitting diode lighting apparatus' [patent_app_type] => utility [patent_app_number] => 13/272043 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2610 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272043 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272043
Organic light emitting diode lighting apparatus Oct 11, 2011 Issued
Array ( [id] => 9455804 [patent_doc_number] => 08716816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'SOI-based CMUT device with buried electrodes' [patent_app_type] => utility [patent_app_number] => 13/272054 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 59 [patent_no_of_words] => 4106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272054 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272054
SOI-based CMUT device with buried electrodes Oct 11, 2011 Issued
Array ( [id] => 8910035 [patent_doc_number] => 08482102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/317168 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 6088 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13317168 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/317168
Semiconductor device Oct 11, 2011 Issued
Array ( [id] => 7815168 [patent_doc_number] => 20120061788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'PHOTODIODES WITH PN-JUNCTION ON BOTH FRONT AND BACK SIDES' [patent_app_type] => utility [patent_app_number] => 13/225245 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061788.pdf [firstpage_image] =>[orig_patent_app_number] => 13225245 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/225245
PHOTODIODES WITH PN-JUNCTION ON BOTH FRONT AND BACK SIDES Sep 1, 2011 Abandoned
Array ( [id] => 10045440 [patent_doc_number] => 09085829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Electrodeposition of thin-film cells containing non-toxic elements' [patent_app_type] => utility [patent_app_number] => 13/222266 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2456 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222266 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222266
Electrodeposition of thin-film cells containing non-toxic elements Aug 30, 2011 Issued
Array ( [id] => 7586907 [patent_doc_number] => 20110281417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'VAPOR DEPOSITION OF SILICON DIOXIDE NANOLAMINATES' [patent_app_type] => utility [patent_app_number] => 13/189283 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12183 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20110281417.pdf [firstpage_image] =>[orig_patent_app_number] => 13189283 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189283
Vapor deposition of silicon dioxide nanolaminates Jul 21, 2011 Issued
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