Search

Kevin V. Quinto

Examiner (ID: 8233, Phone: (571)272-1920 , Office: P/2817 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2817, 2821, 2829, 2893
Total Applications
1390
Issued Applications
1170
Pending Applications
65
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9676771 [patent_doc_number] => 08815680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Non-volatile memory having nano crystalline silicon hillocks floating gate' [patent_app_type] => utility [patent_app_number] => 12/886534 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 5589 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12886534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/886534
Non-volatile memory having nano crystalline silicon hillocks floating gate Sep 19, 2010 Issued
Array ( [id] => 6096588 [patent_doc_number] => 20110003444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS' [patent_app_type] => utility [patent_app_number] => 12/883096 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20110003444.pdf [firstpage_image] =>[orig_patent_app_number] => 12883096 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883096
Process of forming an electronic device including insulating layers having different strains Sep 14, 2010 Issued
Array ( [id] => 8764893 [patent_doc_number] => 20130092931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'THIN FILM TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 13/704012 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13704012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/704012
Thin film transistors Jul 1, 2010 Issued
Array ( [id] => 8205223 [patent_doc_number] => 20120126377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/321960 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126377.pdf [firstpage_image] =>[orig_patent_app_number] => 13321960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/321960
Semiconductor device May 13, 2010 Issued
Array ( [id] => 9937298 [patent_doc_number] => 08987103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/776674 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7849 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12776674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776674
Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device May 9, 2010 Issued
Array ( [id] => 9711461 [patent_doc_number] => 08836036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Method for fabricating semiconductor devices using stress engineering' [patent_app_type] => utility [patent_app_number] => 12/776437 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6832 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12776437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776437
Method for fabricating semiconductor devices using stress engineering May 9, 2010 Issued
Array ( [id] => 9692551 [patent_doc_number] => 08823154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Encapsulation architectures for utilizing flexible barrier films' [patent_app_type] => utility [patent_app_number] => 12/800098 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13835 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12800098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800098
Encapsulation architectures for utilizing flexible barrier films May 6, 2010 Issued
Array ( [id] => 6105763 [patent_doc_number] => 20110186806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'Doped graphene electronic materials' [patent_app_type] => utility [patent_app_number] => 12/800058 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12263 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186806.pdf [firstpage_image] =>[orig_patent_app_number] => 12800058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800058
Doped graphene electronic materials May 6, 2010 Issued
Array ( [id] => 6484754 [patent_doc_number] => 20100258915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/757151 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258915.pdf [firstpage_image] =>[orig_patent_app_number] => 12757151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757151
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Apr 8, 2010 Abandoned
Array ( [id] => 6484045 [patent_doc_number] => 20100258848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'COMPENSATED GATE MISFET AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/756906 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2509 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258848.pdf [firstpage_image] =>[orig_patent_app_number] => 12756906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756906
Compensated gate MISFET and method for fabricating the same Apr 7, 2010 Issued
Array ( [id] => 8364180 [patent_doc_number] => 08253247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/756208 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 8152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756208
Semiconductor device and method for manufacturing the same Apr 7, 2010 Issued
Array ( [id] => 8652929 [patent_doc_number] => 08372675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Microelectronic device and fabricating method thereof and MEMS package structure and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 12/756558 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756558
Microelectronic device and fabricating method thereof and MEMS package structure and fabricating method thereof Apr 7, 2010 Issued
Array ( [id] => 7479806 [patent_doc_number] => 20110248263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'INTEGRATED CIRCUITS HAVING BACKSIDE TEST STRUCTURES AND METHODS FOR THE FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 12/755983 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248263.pdf [firstpage_image] =>[orig_patent_app_number] => 12755983 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755983
Integrated circuits having backside test structures and methods for the fabrication thereof Apr 6, 2010 Issued
Array ( [id] => 10844976 [patent_doc_number] => 08872154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Field effect transistor fabrication from carbon nanotubes' [patent_app_type] => utility [patent_app_number] => 12/755188 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 82 [patent_no_of_words] => 22320 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12755188 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755188
Field effect transistor fabrication from carbon nanotubes Apr 5, 2010 Issued
Array ( [id] => 8071675 [patent_doc_number] => 20110241185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION' [patent_app_type] => utility [patent_app_number] => 12/754108 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10771 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241185.pdf [firstpage_image] =>[orig_patent_app_number] => 12754108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754108
SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION Apr 4, 2010 Abandoned
Array ( [id] => 8071929 [patent_doc_number] => 20110241059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'LED DIE STRUCTURE AND METHOD FOR MANUFACTURING THE BOTTOM TERMINAL THEREOF' [patent_app_type] => utility [patent_app_number] => 12/749816 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1728 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241059.pdf [firstpage_image] =>[orig_patent_app_number] => 12749816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749816
LED DIE STRUCTURE AND METHOD FOR MANUFACTURING THE BOTTOM TERMINAL THEREOF Mar 29, 2010 Abandoned
Array ( [id] => 8072139 [patent_doc_number] => 20110240953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'INTEGRATED SEMICONDUCTOR NANOWIRE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/749872 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20110240953.pdf [firstpage_image] =>[orig_patent_app_number] => 12749872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749872
Integrated semiconductor nanowire device Mar 29, 2010 Issued
Array ( [id] => 8071933 [patent_doc_number] => 20110241058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'LED HEAT DISSIPATING MODULE' [patent_app_type] => utility [patent_app_number] => 12/749815 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241058.pdf [firstpage_image] =>[orig_patent_app_number] => 12749815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749815
LED HEAT DISSIPATING MODULE Mar 29, 2010 Abandoned
Array ( [id] => 9626427 [patent_doc_number] => 08796106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Isolation trenches' [patent_app_type] => utility [patent_app_number] => 12/749866 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4139 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749866
Isolation trenches Mar 29, 2010 Issued
Array ( [id] => 8549108 [patent_doc_number] => 08323989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/749805 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8816 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749805 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749805
Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices Mar 29, 2010 Issued
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