
Kevin Worrell
Examiner (ID: 15304)
| Most Active Art Unit | 1789 |
| Art Unit(s) | 1789 |
| Total Applications | 364 |
| Issued Applications | 31 |
| Pending Applications | 71 |
| Abandoned Applications | 280 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10624482
[patent_doc_number] => 09343432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-17
[patent_title] => 'Semiconductor chip stack having improved encapsulation'
[patent_app_type] => utility
[patent_app_number] => 14/094996
[patent_app_country] => US
[patent_app_date] => 2013-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 40
[patent_no_of_words] => 14269
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094996
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/094996 | Semiconductor chip stack having improved encapsulation | Dec 2, 2013 | Issued |
Array
(
[id] => 9639466
[patent_doc_number] => 20140217576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-07
[patent_title] => 'SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/095376
[patent_app_country] => US
[patent_app_date] => 2013-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10321
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095376
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/095376 | Semiconductor package with thermal dissipating member and method of manufacturing the same | Dec 2, 2013 | Issued |
Array
(
[id] => 11898453
[patent_doc_number] => 09768398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'Substrate for organic electronic device'
[patent_app_type] => utility
[patent_app_number] => 14/441143
[patent_app_country] => US
[patent_app_date] => 2013-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 10208
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441143
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/441143 | Substrate for organic electronic device | Dec 1, 2013 | Issued |
Array
(
[id] => 9508200
[patent_doc_number] => 20140144690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'METHOD FOR PRODUCING A STRUCTURE FOR MICROELECTRONIC DEVICE ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 14/090321
[patent_app_country] => US
[patent_app_date] => 2013-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4145
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090321
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/090321 | Method for producing a structure for microelectronic device assembly | Nov 25, 2013 | Issued |
Array
(
[id] => 9905952
[patent_doc_number] => 20150061152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-05
[patent_title] => 'PACKAGE MODULE WITH OFFSET STACK DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/088915
[patent_app_country] => US
[patent_app_date] => 2013-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 9951
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088915
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/088915 | PACKAGE MODULE WITH OFFSET STACK DEVICE | Nov 24, 2013 | Abandoned |
Array
(
[id] => 10165350
[patent_doc_number] => 09196582
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-24
[patent_title] => 'Word line coupling prevention using 3D integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 14/087016
[patent_app_country] => US
[patent_app_date] => 2013-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5567
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087016
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/087016 | Word line coupling prevention using 3D integrated circuit | Nov 21, 2013 | Issued |
Array
(
[id] => 9855147
[patent_doc_number] => 20150035165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-05
[patent_title] => 'INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/086995
[patent_app_country] => US
[patent_app_date] => 2013-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4458
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086995
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/086995 | INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE | Nov 21, 2013 | Abandoned |
Array
(
[id] => 9508857
[patent_doc_number] => 20140145348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'RF (RADIO FREQUENCY) MODULE AND METHOD OF MAUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/087827
[patent_app_country] => US
[patent_app_date] => 2013-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2869
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087827
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/087827 | RF (RADIO FREQUENCY) MODULE AND METHOD OF MAUFACTURING THE SAME | Nov 21, 2013 | Abandoned |
Array
(
[id] => 10537759
[patent_doc_number] => 09263394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Multiple bond via arrays of different wire heights on a same substrate'
[patent_app_type] => utility
[patent_app_number] => 14/087252
[patent_app_country] => US
[patent_app_date] => 2013-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 49
[patent_no_of_words] => 10060
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/087252 | Multiple bond via arrays of different wire heights on a same substrate | Nov 21, 2013 | Issued |
Array
(
[id] => 10252358
[patent_doc_number] => 20150137354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'PILLAR BUMP FORMED USING SPOT-LASER'
[patent_app_type] => utility
[patent_app_number] => 14/086932
[patent_app_country] => US
[patent_app_date] => 2013-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3321
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086932
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/086932 | Pillar bump formed using spot-laser | Nov 20, 2013 | Issued |
Array
(
[id] => 10138488
[patent_doc_number] => 09171810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-27
[patent_title] => 'Electronic device incorporating a randomized interconnection layer having a randomized conduction pattern'
[patent_app_type] => utility
[patent_app_number] => 14/086601
[patent_app_country] => US
[patent_app_date] => 2013-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 4087
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086601
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/086601 | Electronic device incorporating a randomized interconnection layer having a randomized conduction pattern | Nov 20, 2013 | Issued |
Array
(
[id] => 9367519
[patent_doc_number] => 20140077392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/085124
[patent_app_country] => US
[patent_app_date] => 2013-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 16286
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085124
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/085124 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Nov 19, 2013 | Abandoned |
Array
(
[id] => 10217487
[patent_doc_number] => 20150102481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'SINTERED BACKSIDE SHIM IN A PRESS PACK CASSETTE'
[patent_app_type] => utility
[patent_app_number] => 14/054754
[patent_app_country] => US
[patent_app_date] => 2013-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9017
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054754
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/054754 | Sintered backside shim in a press pack cassette | Oct 14, 2013 | Issued |
Array
(
[id] => 9965423
[patent_doc_number] => 09013040
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-04-21
[patent_title] => 'Memory device with die stacking and heat dissipation'
[patent_app_type] => utility
[patent_app_number] => 14/045226
[patent_app_country] => US
[patent_app_date] => 2013-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 2855
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045226
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/045226 | Memory device with die stacking and heat dissipation | Oct 2, 2013 | Issued |
Array
(
[id] => 9951789
[patent_doc_number] => 09000583
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Multiple die in a face down package'
[patent_app_type] => utility
[patent_app_number] => 14/040948
[patent_app_country] => US
[patent_app_date] => 2013-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 7168
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040948
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/040948 | Multiple die in a face down package | Sep 29, 2013 | Issued |
Array
(
[id] => 9984279
[patent_doc_number] => 09029995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-12
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 14/037489
[patent_app_country] => US
[patent_app_date] => 2013-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 39
[patent_no_of_words] => 19955
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 312
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037489
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/037489 | Semiconductor device and method of manufacturing the same | Sep 25, 2013 | Issued |
Array
(
[id] => 10597315
[patent_doc_number] => 09318410
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'Cooling assembly using heatspreader'
[patent_app_type] => utility
[patent_app_number] => 14/037706
[patent_app_country] => US
[patent_app_date] => 2013-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1804
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037706
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/037706 | Cooling assembly using heatspreader | Sep 25, 2013 | Issued |
Array
(
[id] => 10125324
[patent_doc_number] => 09159690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Tall solders for through-mold interconnect'
[patent_app_type] => utility
[patent_app_number] => 14/036755
[patent_app_country] => US
[patent_app_date] => 2013-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 41
[patent_no_of_words] => 6214
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036755
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/036755 | Tall solders for through-mold interconnect | Sep 24, 2013 | Issued |
Array
(
[id] => 10525557
[patent_doc_number] => 09252077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Package vias for radio frequency antenna connections'
[patent_app_type] => utility
[patent_app_number] => 14/037213
[patent_app_country] => US
[patent_app_date] => 2013-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 6448
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037213
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/037213 | Package vias for radio frequency antenna connections | Sep 24, 2013 | Issued |
Array
(
[id] => 10577000
[patent_doc_number] => 09299650
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-03-29
[patent_title] => 'Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 14/037274
[patent_app_country] => US
[patent_app_date] => 2013-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 22
[patent_no_of_words] => 9790
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037274
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/037274 | Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof | Sep 24, 2013 | Issued |