Khamdan N. Alrobaie

Array ( [id] => 20765740 [patent_doc_number] => 20260162727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-11 [patent_title] => MEMORY DEVICE AND PROGRAM OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 19/011443 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20283363 [patent_doc_number] => 20250308605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => PROGRAM ERROR HANDLING AT A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/984995 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20501659 [patent_doc_number] => 20260031121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => MEMORY DEVICE AND WORD LINE SIGNAL GENERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/969311 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20642353 [patent_doc_number] => 20260100713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-09 [patent_title] => DELAY LOCKED LOOP DEVICE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/947210 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773113 [patent_doc_number] => 20250054539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD OF PROGRAMMING MEMORY DEVICE AND RELATED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/933326 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18933326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773127 [patent_doc_number] => 20250054553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/930319 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773105 [patent_doc_number] => 20250054531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES [patent_app_type] => utility [patent_app_number] => 18/930833 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19757804 [patent_doc_number] => 20250046369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => DRIFT COMPENSATION FOR CODEWORDS IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/924813 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19749201 [patent_doc_number] => 20250037766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 18/919268 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20852337 [patent_doc_number] => 12689380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-21 [patent_title] => Delay locked loop device and method for operating the same [patent_app_type] => utility [patent_app_number] => 18/909128 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5793 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20629348 [patent_doc_number] => 20260093634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => NON-ADJACENT CONNECTION OF HIGH-BANDWIDTH MEMORY CHIPLETS, I/O CHIPLETS, AND COMPUTE CHIPLETS THROUGH EMBEDDED LOGIC BRIDGES [patent_app_type] => utility [patent_app_number] => 18/903427 [patent_app_country] => US [patent_app_date] => 2024-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18903427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20235505 [patent_doc_number] => 20250292824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/897025 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20618014 [patent_doc_number] => 20260088117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => SYNCHRONIZATION POINTS BASED PARAMETER TUNING IN A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/894234 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19686125 [patent_doc_number] => 20250004670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MEMORY MODULE INTERFACES [patent_app_type] => utility [patent_app_number] => 18/886242 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20311728 [patent_doc_number] => 20250329357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY SYSTEM AND MEMORY OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 18/884372 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20096095 [patent_doc_number] => 20250226031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/829771 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20252796 [patent_doc_number] => 20250301665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/824795 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773126 [patent_doc_number] => 20250054552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => DEVICE AND METHOD TO GENERATE BIAS VOLTAGES IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/807792 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18807792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20704055 [patent_doc_number] => 12626770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Control gate voltage generating circuit for non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/795606 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3209 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19604423 [patent_doc_number] => 20240395303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY [patent_app_type] => utility [patent_app_number] => 18/794453 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794453 [rel_patent_id] =>[rel_patent_doc_number] =>)