Khamdan N. Alrobaie

Array ( [id] => 19696069 [patent_doc_number] => 20250014614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 18/490922 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18942292 [patent_doc_number] => 20240037431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 18/484233 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19237061 [patent_doc_number] => 20240194256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => WORD LINE DRIVERS FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/373490 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20266796 [patent_doc_number] => 12437792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Data logic processing circuit integrated in a data storage circuit [patent_app_type] => utility [patent_app_number] => 18/373231 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4474 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20274680 [patent_doc_number] => 12444464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Resistive memory device and method of operating the resistive memory device [patent_app_type] => utility [patent_app_number] => 18/468500 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7625 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19835465 [patent_doc_number] => 20250087251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Power-Gate Structure [patent_app_type] => utility [patent_app_number] => 18/367902 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19757807 [patent_doc_number] => 20250046372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY AND MEMORY MINI-ARRAY THEREOF WITH IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/367488 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20145515 [patent_doc_number] => 12379857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Dynamic peak power management for multi-die operations [patent_app_type] => utility [patent_app_number] => 18/367120 [patent_app_country] => US [patent_app_date] => 2023-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19820715 [patent_doc_number] => 20250078922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => IN-MEMORY COMPUTATION SYSTEM USING A SEGMENTED MEMORY ARCHITECTURE WITH LOCAL MEMORY ARRAY SELECTION FOR SIMULTANEOUSLY PERFORMING MULTIPLE INDEPENDENT OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/241812 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19467667 [patent_doc_number] => 20240321337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => POWER CONTROL CIRCUIT FOR MEMORY CIRCUIT BASED ON COMPLEMENTARY FIELD EFFECT TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/455876 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007409 [patent_doc_number] => 20240071480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PROCESS AND TEMPERATURE COMPENSATED WORD LINE UNDERDRIVE SCHEME FOR SRAM [patent_app_type] => utility [patent_app_number] => 18/231461 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19363943 [patent_doc_number] => 20240265977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => FLASH MEMORY FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SAMPLING SWITCH CIRCUIT AND SENSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/366368 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19943427 [patent_doc_number] => 12315563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory apparatus using semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/231053 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 6865 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007392 [patent_doc_number] => 20240071463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => VOLTAGE GENERATING CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/364481 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20111287 [patent_doc_number] => 12362022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Scheduled interrupts for peak power management token ring communication [patent_app_type] => utility [patent_app_number] => 18/229249 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19626858 [patent_doc_number] => 12165705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Memory cell array circuit and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/362863 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 15185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18905765 [patent_doc_number] => 20240021250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/362221 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19712349 [patent_doc_number] => 20250022491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SYSTEM FOR SAVING LEAKAGE POWER IN STATIC RANDOM ACCESS MEMORY (SRAM) USING LIGHT SLEEP MODE [patent_app_type] => utility [patent_app_number] => 18/352625 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18729097 [patent_doc_number] => 20230343392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 18/214714 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19523014 [patent_doc_number] => 12124741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Memory module interfaces [patent_app_type] => utility [patent_app_number] => 18/340589 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340589 [rel_patent_id] =>[rel_patent_doc_number] =>)