Search

Khang D. Do

Examiner (ID: 7245, Phone: (571)270-7837 , Office: P/2492 )

Most Active Art Unit
2492
Art Unit(s)
2492, 2496
Total Applications
472
Issued Applications
395
Pending Applications
28
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19467707 [patent_doc_number] => 20240321377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO [patent_app_type] => utility [patent_app_number] => 18/737631 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737631
SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO Jun 6, 2024 Pending
Array ( [id] => 19451104 [patent_doc_number] => 20240311234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SECURE ERROR CORRECTING CODE (ECC) TRUST EXECUTION ENVIRONMENT (TEE) CONFIGURATION METADATA ENCODING [patent_app_type] => utility [patent_app_number] => 18/676811 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676811
SECURE ERROR CORRECTING CODE (ECC) TRUST EXECUTION ENVIRONMENT (TEE) CONFIGURATION METADATA ENCODING May 28, 2024 Pending
Array ( [id] => 19788280 [patent_doc_number] => 20250061959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR APPARATUS HAVING TEST FUNCTION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/619671 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619671
SEMICONDUCTOR APPARATUS HAVING TEST FUNCTION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME Mar 27, 2024 Pending
Array ( [id] => 19285375 [patent_doc_number] => 20240221852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Multi-Mode Memory Module with Data Handlers [patent_app_type] => utility [patent_app_number] => 18/402549 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402549
Multi-mode memory subsystem including control and data modules for buffering and testing Jan 1, 2024 Issued
Array ( [id] => 19285375 [patent_doc_number] => 20240221852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Multi-Mode Memory Module with Data Handlers [patent_app_type] => utility [patent_app_number] => 18/402549 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402549
Multi-mode memory subsystem including control and data modules for buffering and testing Jan 1, 2024 Issued
Array ( [id] => 19056605 [patent_doc_number] => 20240098574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INFORMATION PROCESSING DEVICE, COMMUNICATION SYSTEM, AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/522228 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522228
INFORMATION PROCESSING DEVICE, COMMUNICATION SYSTEM, AND INFORMATION PROCESSING METHOD Nov 28, 2023 Pending
Array ( [id] => 19036463 [patent_doc_number] => 20240086278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Low-Overhead, Bidirectional Error Checking for a Serial Peripheral Interface [patent_app_type] => utility [patent_app_number] => 18/512754 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512754
Low-overhead, bidirectional error checking for a serial peripheral interface Nov 16, 2023 Issued
Array ( [id] => 19970702 [patent_doc_number] => 12339305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Method and system for real time outlier detection and product re-binning [patent_app_type] => utility [patent_app_number] => 18/511705 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1223 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511705
Method and system for real time outlier detection and product re-binning Nov 15, 2023 Issued
Array ( [id] => 20010881 [patent_doc_number] => 20250149103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => DETERMINISTIC TEST PROGRAM GENERATION FOR EVALUATING CACHE COHERENCY [patent_app_type] => utility [patent_app_number] => 18/501111 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501111
DETERMINISTIC TEST PROGRAM GENERATION FOR EVALUATING CACHE COHERENCY Nov 2, 2023 Pending
Array ( [id] => 19335358 [patent_doc_number] => 20240249788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/451969 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451969
MEMORY DEVICE Aug 17, 2023 Pending
Array ( [id] => 18989788 [patent_doc_number] => 20240061757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => METHOD AND SYSTEM FOR ESTABLISHING DATA TRANSFER PROCESSES BETWEEN COMPONENTS OF A TEST SYSTEM [patent_app_type] => utility [patent_app_number] => 18/450293 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450293
METHOD AND SYSTEM FOR ESTABLISHING DATA TRANSFER PROCESSES BETWEEN COMPONENTS OF A TEST SYSTEM Aug 14, 2023 Pending
Array ( [id] => 19603077 [patent_doc_number] => 20240393957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => APPARATUS AND METHOD FOR TWO-STEP READ OF RESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/355368 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355368
APPARATUS AND METHOD FOR TWO-STEP READ OF RESISTIVE RANDOM ACCESS MEMORY Jul 18, 2023 Pending
Array ( [id] => 18897238 [patent_doc_number] => 20240012723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM [patent_app_type] => utility [patent_app_number] => 18/352744 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352744
HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM Jul 13, 2023 Pending
Array ( [id] => 18897238 [patent_doc_number] => 20240012723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM [patent_app_type] => utility [patent_app_number] => 18/352744 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352744
HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM Jul 13, 2023 Pending
Array ( [id] => 18740990 [patent_doc_number] => 20230349970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/348110 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348110
In system test of chips in functional systems Jul 5, 2023 Issued
Array ( [id] => 19219953 [patent_doc_number] => 20240184657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => STORAGE DEVICE FOR SETTING OPERATION PARAMETERS FOR RANDOM ACCESS MEMORY UPON POWER-ON AND OPERATION [patent_app_type] => utility [patent_app_number] => 18/335137 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335137
Storage device for setting operation parameters for random access memory upon power-on and operation Jun 14, 2023 Issued
Array ( [id] => 19590755 [patent_doc_number] => 20240388312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => FAST EFFICIENT DECODER FOR LOW DISTANCE RS AND BCH CODES [patent_app_type] => utility [patent_app_number] => 18/198636 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198636
FAST EFFICIENT DECODER FOR LOW DISTANCE RS AND BCH CODES May 16, 2023 Pending
Array ( [id] => 18584652 [patent_doc_number] => 20230266916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY CONTROLLER, STORAGE DEVICE AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/310978 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310978
Memory controller, storage device and operating method of memory controller May 1, 2023 Issued
Array ( [id] => 18584652 [patent_doc_number] => 20230266916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY CONTROLLER, STORAGE DEVICE AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/310978 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310978
Memory controller, storage device and operating method of memory controller May 1, 2023 Issued
Array ( [id] => 19943445 [patent_doc_number] => 12315581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory system, memory controller and method for operating memory system [patent_app_type] => utility [patent_app_number] => 18/184679 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184679
Memory system, memory controller and method for operating memory system Mar 15, 2023 Issued
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