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Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10259908 [patent_doc_number] => 20150144905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'ARRAY SUBSTRATE FOR DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/475182 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5992 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475182 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475182
Array substrate for display device Sep 1, 2014 Issued
Array ( [id] => 9559661 [patent_doc_number] => 20140177373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SYSTEM INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES' [patent_app_type] => utility [patent_app_number] => 14/190514 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2411 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190514 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190514
System involving electrically reprogrammable fuses Feb 25, 2014 Issued
Array ( [id] => 10086289 [patent_doc_number] => 09123642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-01 [patent_title] => 'Method of forming drain extended MOS transistors for high voltage circuits' [patent_app_type] => utility [patent_app_number] => 14/108967 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108967 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/108967
Method of forming drain extended MOS transistors for high voltage circuits Dec 16, 2013 Issued
Array ( [id] => 9291371 [patent_doc_number] => 20140035005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'Monolithic Integrated Group III-V and Group IV Device' [patent_app_type] => utility [patent_app_number] => 14/049564 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14049564 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/049564
Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device Oct 8, 2013 Issued
Array ( [id] => 10870145 [patent_doc_number] => 08895340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Biosensor and system and process for forming' [patent_app_type] => utility [patent_app_number] => 14/022315 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 4678 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14022315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/022315
Biosensor and system and process for forming Sep 9, 2013 Issued
Array ( [id] => 9762146 [patent_doc_number] => 08846467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Silicidation of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/021525 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4897 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021525 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021525
Silicidation of semiconductor devices Sep 8, 2013 Issued
Array ( [id] => 10844439 [patent_doc_number] => 08871615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/021324 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 3062 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021324 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021324
Method of manufacturing semiconductor device Sep 8, 2013 Issued
Array ( [id] => 9901593 [patent_doc_number] => 20150056793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'DOPING OF A SUBSTRATE VIA A DOPANT CONTAINING POLYMER FILM' [patent_app_type] => utility [patent_app_number] => 13/972307 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4923 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972307 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/972307
Doping of a substrate via a dopant containing polymer film Aug 20, 2013 Issued
Array ( [id] => 9692555 [patent_doc_number] => 08823159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Stacked microelectronic devices' [patent_app_type] => utility [patent_app_number] => 13/933607 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5486 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933607
Stacked microelectronic devices Jul 1, 2013 Issued
Array ( [id] => 10844415 [patent_doc_number] => 08871592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Method of manufacturing a semiconductor device including concave portion' [patent_app_type] => utility [patent_app_number] => 13/926109 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 58 [patent_no_of_words] => 11487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926109
Method of manufacturing a semiconductor device including concave portion Jun 24, 2013 Issued
Array ( [id] => 9440791 [patent_doc_number] => 08709901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method of forming an isolation structure' [patent_app_type] => utility [patent_app_number] => 13/864277 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3448 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864277 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/864277
Method of forming an isolation structure Apr 16, 2013 Issued
Array ( [id] => 9575082 [patent_doc_number] => 08765495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method of forming pattern of doped region' [patent_app_type] => utility [patent_app_number] => 13/863397 [patent_app_country] => US [patent_app_date] => 2013-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4276 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863397 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/863397
Method of forming pattern of doped region Apr 15, 2013 Issued
Array ( [id] => 9427483 [patent_doc_number] => 08703557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Methods of removing dummy fin structures when forming finFET devices' [patent_app_type] => utility [patent_app_number] => 13/863044 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 7080 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863044 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/863044
Methods of removing dummy fin structures when forming finFET devices Apr 14, 2013 Issued
Array ( [id] => 9648552 [patent_doc_number] => 08802561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Method of inhibiting wire collapse' [patent_app_type] => utility [patent_app_number] => 13/862222 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 44 [patent_no_of_words] => 13078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862222
Method of inhibiting wire collapse Apr 11, 2013 Issued
Array ( [id] => 9427537 [patent_doc_number] => 08703611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Method for manufacturing a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 13/861459 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/861459
Method for manufacturing a semiconductor structure Apr 11, 2013 Issued
Array ( [id] => 10905792 [patent_doc_number] => 20140308805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Method of In-Line Diffusion for Solar Cells' [patent_app_type] => utility [patent_app_number] => 13/861537 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3311 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/861537
Method of in-line diffusion for solar cells Apr 11, 2013 Issued
Array ( [id] => 10850926 [patent_doc_number] => 08877605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-04 [patent_title] => 'Silicon substrate fabrication' [patent_app_type] => utility [patent_app_number] => 13/860557 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 4653 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860557
Silicon substrate fabrication Apr 10, 2013 Issued
Array ( [id] => 9455143 [patent_doc_number] => 08716150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Method of forming a low-K dielectric film' [patent_app_type] => utility [patent_app_number] => 13/860603 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860603
Method of forming a low-K dielectric film Apr 10, 2013 Issued
Array ( [id] => 9785841 [patent_doc_number] => 20140302661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/859013 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859013
Contact isolation scheme for thin buried oxide substrate devices Apr 8, 2013 Issued
Array ( [id] => 9785866 [patent_doc_number] => 20140302686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'Apparatus and Method for Conformal Treatment of Dielectric Films Using Inductively Coupled Plasma' [patent_app_type] => utility [patent_app_number] => 13/858922 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858922
Method for conformal treatment of dielectric films using inductively coupled plasma Apr 7, 2013 Issued
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