Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1076957 [patent_doc_number] => 07615470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method of manufacturing gallium nitride semiconductor' [patent_app_type] => utility [patent_app_number] => 11/302957 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615470.pdf [firstpage_image] =>[orig_patent_app_number] => 11302957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302957
Method of manufacturing gallium nitride semiconductor Dec 12, 2005 Issued
Array ( [id] => 8955819 [patent_doc_number] => 08501591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method for manufacturing a multiple-bit-per-cell memory' [patent_app_type] => utility [patent_app_number] => 11/285614 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 10037 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11285614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285614
Method for manufacturing a multiple-bit-per-cell memory Nov 20, 2005 Issued
Array ( [id] => 4711241 [patent_doc_number] => 20080299767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Method for Forming a Semiconductor Device Having a Salicide Layer' [patent_app_type] => utility [patent_app_number] => 12/094570 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299767.pdf [firstpage_image] =>[orig_patent_app_number] => 12094570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/094570
Method for Forming a Semiconductor Device Having a Salicide Layer Nov 20, 2005 Abandoned
Array ( [id] => 5512126 [patent_doc_number] => 20090212430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'CARBON NANOTUBE-BASED CONDUCTIVE CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES' [patent_app_type] => utility [patent_app_number] => 11/718712 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4574 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212430.pdf [firstpage_image] =>[orig_patent_app_number] => 11718712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718712
Carbon nanotube-based conductive connections for integrated circuit devices Nov 3, 2005 Issued
Array ( [id] => 4507325 [patent_doc_number] => 07915179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Insulating film forming method and substrate processing method' [patent_app_type] => utility [patent_app_number] => 11/718582 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 14916 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915179.pdf [firstpage_image] =>[orig_patent_app_number] => 11718582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718582
Insulating film forming method and substrate processing method Nov 1, 2005 Issued
Array ( [id] => 813655 [patent_doc_number] => 07413927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-19 [patent_title] => 'Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages' [patent_app_type] => utility [patent_app_number] => 11/264604 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413927.pdf [firstpage_image] =>[orig_patent_app_number] => 11264604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264604
Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages Oct 30, 2005 Issued
Array ( [id] => 408120 [patent_doc_number] => 07285437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Method of separating MEMS devices from a composite structure' [patent_app_type] => utility [patent_app_number] => 11/273271 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1497 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285437.pdf [firstpage_image] =>[orig_patent_app_number] => 11273271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273271
Method of separating MEMS devices from a composite structure Oct 27, 2005 Issued
Array ( [id] => 5710580 [patent_doc_number] => 20060051925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Atomic layer deposition of metal oxynitride layers as gate dielectrics' [patent_app_type] => utility [patent_app_number] => 11/253542 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4072 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20060051925.pdf [firstpage_image] =>[orig_patent_app_number] => 11253542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253542
Atomic layer deposition of metal oxynitride layers as gate dielectrics Oct 18, 2005 Abandoned
Array ( [id] => 5820583 [patent_doc_number] => 20060024896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'METHOD FOR FABRICATING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH SELECTIVE EPITAXIAL GROWTH FILM' [patent_app_type] => utility [patent_app_number] => 11/163317 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2305 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20060024896.pdf [firstpage_image] =>[orig_patent_app_number] => 11163317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163317
METHOD FOR FABRICATING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH SELECTIVE EPITAXIAL GROWTH FILM Oct 13, 2005 Abandoned
Array ( [id] => 4695531 [patent_doc_number] => 20080217715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Wafer Level Package Using Silicon Via Contacts for Cmos Image Sensor and Method of Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 12/088529 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2744 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217715.pdf [firstpage_image] =>[orig_patent_app_number] => 12088529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/088529
Wafer Level Package Using Silicon Via Contacts for Cmos Image Sensor and Method of Fabricating the Same Oct 10, 2005 Abandoned
Array ( [id] => 5588809 [patent_doc_number] => 20060038260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Semiconductor wafer and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/245059 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5769 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038260.pdf [firstpage_image] =>[orig_patent_app_number] => 11245059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245059
Semiconductor wafer having a separation portion on a peripheral area Oct 6, 2005 Issued
Array ( [id] => 4510398 [patent_doc_number] => 07915622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Textured light emitting diodes' [patent_app_type] => utility [patent_app_number] => 11/576151 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2815 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915622.pdf [firstpage_image] =>[orig_patent_app_number] => 11576151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/576151
Textured light emitting diodes Sep 26, 2005 Issued
Array ( [id] => 5720900 [patent_doc_number] => 20060073675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Semiconductor device and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/232337 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2418 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20060073675.pdf [firstpage_image] =>[orig_patent_app_number] => 11232337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232337
Semiconductor device and method of manufacturing thereof Sep 20, 2005 Abandoned
Array ( [id] => 4775820 [patent_doc_number] => 20080283818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Semiconductor Heterostructure' [patent_app_type] => utility [patent_app_number] => 11/663142 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4803 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283818.pdf [firstpage_image] =>[orig_patent_app_number] => 11663142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/663142
Semiconductor heterostructure Sep 18, 2005 Issued
Array ( [id] => 5710582 [patent_doc_number] => 20060051927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Manufacture of insulated gate type field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/219567 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12503 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20060051927.pdf [firstpage_image] =>[orig_patent_app_number] => 11219567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219567
Manufacture of insulated gate type field effect transistor Sep 1, 2005 Issued
Array ( [id] => 5793636 [patent_doc_number] => 20060014317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Integrated circuit package having reduced interconnects' [patent_app_type] => utility [patent_app_number] => 11/218998 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014317.pdf [firstpage_image] =>[orig_patent_app_number] => 11218998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218998
Methods of forming an integrated circuit package Aug 31, 2005 Issued
Array ( [id] => 5894932 [patent_doc_number] => 20060003471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Self-aligned, low-resistance, efficient memory array' [patent_app_type] => utility [patent_app_number] => 11/212646 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3498 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003471.pdf [firstpage_image] =>[orig_patent_app_number] => 11212646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212646
Self-aligned, low-resistance, efficient memory array Aug 28, 2005 Issued
Array ( [id] => 856742 [patent_doc_number] => 07375001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Semiconductor device and method therefore' [patent_app_type] => utility [patent_app_number] => 11/209057 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4297 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375001.pdf [firstpage_image] =>[orig_patent_app_number] => 11209057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209057
Semiconductor device and method therefore Aug 21, 2005 Issued
Array ( [id] => 5877977 [patent_doc_number] => 20060027817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Light emitting device, semiconductor device, and method of fabricating the devices' [patent_app_type] => utility [patent_app_number] => 11/201087 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15550 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20060027817.pdf [firstpage_image] =>[orig_patent_app_number] => 11201087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201087
Method of fabricating a semiconductor device having a film in contact with a debonded layer Aug 10, 2005 Issued
Array ( [id] => 5771035 [patent_doc_number] => 20050266635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Graded GexSe100-x concentration in PCRAM' [patent_app_type] => utility [patent_app_number] => 11/195642 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5340 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20050266635.pdf [firstpage_image] =>[orig_patent_app_number] => 11195642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195642
Graded GexSe100-x concentration in PCRAM Aug 2, 2005 Issued
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