Khanh B. Duong

Array ( [id] => 408174 [patent_doc_number] => 07285492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Method for processing substrate' [patent_app_type] => utility [patent_app_number] => 11/039967 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 19977 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285492.pdf [firstpage_image] =>[orig_patent_app_number] => 11039967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5820604 [patent_doc_number] => 20060024917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method and system for fabricating strained layers for the manufacture of integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/043477 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6184 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20060024917.pdf [firstpage_image] =>[orig_patent_app_number] => 11043477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4708031 [patent_doc_number] => 20080296557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Semiconductor Power Switch and Method for Producing a Semiconductor Power Switch' [patent_app_type] => utility [patent_app_number] => 10/587062 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4777 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296557.pdf [firstpage_image] =>[orig_patent_app_number] => 10587062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 352593 [patent_doc_number] => 07491614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Methods for forming channel stop for deep trench isolation prior to deep trench etch' [patent_app_type] => utility [patent_app_number] => 10/905627 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2041 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491614.pdf [firstpage_image] =>[orig_patent_app_number] => 10905627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7169066 [patent_doc_number] => 20050121713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/033257 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121713.pdf [firstpage_image] =>[orig_patent_app_number] => 11033257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631673 [patent_doc_number] => 20060148143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'METHOD OF CREATING A Ge-RICH CHANNEL LAYER FOR HIGH-PERFORMANCE CMOS CIRCUITS' [patent_app_type] => utility [patent_app_number] => 10/905477 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148143.pdf [firstpage_image] =>[orig_patent_app_number] => 10905477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7167518 [patent_doc_number] => 20050121111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Thin film semiconductor device having a gate electrode insulator formed through high-heat oxidization' [patent_app_type] => utility [patent_app_number] => 11/031144 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5813 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121111.pdf [firstpage_image] =>[orig_patent_app_number] => 11031144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7039579 [patent_doc_number] => 20050158968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Wafer laser processing method' [patent_app_type] => utility [patent_app_number] => 11/028737 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3855 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158968.pdf [firstpage_image] =>[orig_patent_app_number] => 11028737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631722 [patent_doc_number] => 20060148192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Damascene MIM capacitor structure with self-aligned oxidation fabrication process' [patent_app_type] => utility [patent_app_number] => 11/029727 [patent_app_country] => US [patent_app_date] => 2005-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2507 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148192.pdf [firstpage_image] =>[orig_patent_app_number] => 11029727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 377039 [patent_doc_number] => 07312139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method of fabricating nitrogen-containing gate dielectric layer and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/028717 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2814 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312139.pdf [firstpage_image] =>[orig_patent_app_number] => 11028717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253756 [patent_doc_number] => 20050142841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for forming metal pattern to reduce contact resistivity with interconnection contact' [patent_app_type] => utility [patent_app_number] => 11/024467 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2044 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142841.pdf [firstpage_image] =>[orig_patent_app_number] => 11024467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 710788 [patent_doc_number] => 07056814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Methods of manufacturing a MOS transistor' [patent_app_type] => utility [patent_app_number] => 11/025417 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2546 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/056/07056814.pdf [firstpage_image] =>[orig_patent_app_number] => 11025417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 891934 [patent_doc_number] => 07344945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method of manufacturing a drain side gate trench metal-oxide-semiconductor field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/023327 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 61 [patent_no_of_words] => 11550 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344945.pdf [firstpage_image] =>[orig_patent_app_number] => 11023327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7037089 [patent_doc_number] => 20050156523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Plasma display panel having align marks, and method and apparatus for forming align marks through offset process' [patent_app_type] => utility [patent_app_number] => 11/015787 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156523.pdf [firstpage_image] =>[orig_patent_app_number] => 11015787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 259937 [patent_doc_number] => 07572660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Electrical through-plating of semiconductor chips' [patent_app_type] => utility [patent_app_number] => 11/016617 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3920 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/572/07572660.pdf [firstpage_image] =>[orig_patent_app_number] => 11016617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 439280 [patent_doc_number] => 07259078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Method for forming isolation layer in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/016437 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259078.pdf [firstpage_image] =>[orig_patent_app_number] => 11016437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6905696 [patent_doc_number] => 20050101091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Semiconductor device having a trench isolation and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/011655 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 21040 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101091.pdf [firstpage_image] =>[orig_patent_app_number] => 11011655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5743256 [patent_doc_number] => 20060088981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Wafer packaging and singulation method' [patent_app_type] => utility [patent_app_number] => 11/011640 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3839 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20060088981.pdf [firstpage_image] =>[orig_patent_app_number] => 11011640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 386576 [patent_doc_number] => 07303945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Method for forming pattern of stacked film and thin film transistor' [patent_app_type] => utility [patent_app_number] => 10/999125 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 15737 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/303/07303945.pdf [firstpage_image] =>[orig_patent_app_number] => 10999125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253705 [patent_doc_number] => 20050142828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique' [patent_app_type] => utility [patent_app_number] => 10/987827 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6746 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142828.pdf [firstpage_image] =>[orig_patent_app_number] => 10987827 [rel_patent_id] =>[rel_patent_doc_number] =>)