Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 168219 [patent_doc_number] => 07666756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Methods of fabricating isolation structures in epi-less substrate' [patent_app_type] => utility [patent_app_number] => 10/918314 [patent_app_country] => US [patent_app_date] => 2004-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 123 [patent_no_of_words] => 14880 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/666/07666756.pdf [firstpage_image] =>[orig_patent_app_number] => 10918314 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918314
Methods of fabricating isolation structures in epi-less substrate Aug 13, 2004 Issued
Array ( [id] => 6969702 [patent_doc_number] => 20050035412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Semiconductor fabrication process, lateral PNP transistor, and integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/918057 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4413 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20050035412.pdf [firstpage_image] =>[orig_patent_app_number] => 10918057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918057
Semiconductor fabrication process, lateral PNP transistor, and integrated circuit Aug 12, 2004 Issued
Array ( [id] => 7080587 [patent_doc_number] => 20050045967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method for manufacturing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/916457 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045967.pdf [firstpage_image] =>[orig_patent_app_number] => 10916457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916457
Method for manufacturing semiconductor device including heat treating with a flash lamp Aug 11, 2004 Issued
Array ( [id] => 334250 [patent_doc_number] => 07507661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method of forming narrowly spaced flash memory contact openings and lithography masks' [patent_app_type] => utility [patent_app_number] => 10/916167 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 8013 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/507/07507661.pdf [firstpage_image] =>[orig_patent_app_number] => 10916167 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916167
Method of forming narrowly spaced flash memory contact openings and lithography masks Aug 10, 2004 Issued
Array ( [id] => 840420 [patent_doc_number] => 07390748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Method of forming a polishing inhibiting layer using a slurry having an additive' [patent_app_type] => utility [patent_app_number] => 10/710827 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 4012 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/390/07390748.pdf [firstpage_image] =>[orig_patent_app_number] => 10710827 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710827
Method of forming a polishing inhibiting layer using a slurry having an additive Aug 4, 2004 Issued
Array ( [id] => 694998 [patent_doc_number] => 07071103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Chemical treatment to retard diffusion in a semiconductor overlayer' [patent_app_type] => utility [patent_app_number] => 10/710737 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3764 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071103.pdf [firstpage_image] =>[orig_patent_app_number] => 10710737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710737
Chemical treatment to retard diffusion in a semiconductor overlayer Jul 29, 2004 Issued
Array ( [id] => 826870 [patent_doc_number] => 07402535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Method of incorporating stress into a transistor channel by use of a backside layer' [patent_app_type] => utility [patent_app_number] => 10/902657 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402535.pdf [firstpage_image] =>[orig_patent_app_number] => 10902657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/902657
Method of incorporating stress into a transistor channel by use of a backside layer Jul 27, 2004 Issued
Array ( [id] => 7252872 [patent_doc_number] => 20050074945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => '[OVERLAY MARK AND METHOD OF FABRICATING THE SAME]' [patent_app_type] => utility [patent_app_number] => 10/710637 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5712 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20050074945.pdf [firstpage_image] =>[orig_patent_app_number] => 10710637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710637
Overlay mark and method of fabricating the same Jul 26, 2004 Issued
Array ( [id] => 5768018 [patent_doc_number] => 20060019437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Dual work function gate electrodes obtained through local thickness-limited silicidation' [patent_app_type] => utility [patent_app_number] => 10/897846 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6553 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019437.pdf [firstpage_image] =>[orig_patent_app_number] => 10897846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897846
Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation Jul 22, 2004 Issued
Array ( [id] => 1024520 [patent_doc_number] => 06884669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Hatted polysilicon gate structure for improving salicide performance and method of forming the same' [patent_app_type] => utility [patent_app_number] => 10/894542 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884669.pdf [firstpage_image] =>[orig_patent_app_number] => 10894542 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894542
Hatted polysilicon gate structure for improving salicide performance and method of forming the same Jul 18, 2004 Issued
Array ( [id] => 668394 [patent_doc_number] => 07094634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Structure and method for manufacturing planar SOI substrate with multiple orientations' [patent_app_type] => utility [patent_app_number] => 10/710277 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4357 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/094/07094634.pdf [firstpage_image] =>[orig_patent_app_number] => 10710277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710277
Structure and method for manufacturing planar SOI substrate with multiple orientations Jun 29, 2004 Issued
Array ( [id] => 573732 [patent_doc_number] => 07459384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Preventing cavitation in high aspect ratio dielectric regions of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/710227 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1751 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459384.pdf [firstpage_image] =>[orig_patent_app_number] => 10710227 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710227
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Jun 27, 2004 Issued
Array ( [id] => 7074900 [patent_doc_number] => 20050148168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'METHOD FOR FABRICATING A THROUGH HOLE ON A SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 10/710237 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2532 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148168.pdf [firstpage_image] =>[orig_patent_app_number] => 10710237 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710237
Method for fabricating a through hole on a semiconductor substrate Jun 27, 2004 Issued
Array ( [id] => 7086559 [patent_doc_number] => 20050006671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'System and method based on field-effect transistors for addressing nanometer-scale devices' [patent_app_type] => utility [patent_app_number] => 10/875057 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8847 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006671.pdf [firstpage_image] =>[orig_patent_app_number] => 10875057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875057
Method for making a system for selecting one wire from a plurality of wires Jun 21, 2004 Issued
Array ( [id] => 737168 [patent_doc_number] => 07033898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Method for fabricating a self-aligned bipolar transistor having recessed spacers' [patent_app_type] => utility [patent_app_number] => 10/865153 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5869 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033898.pdf [firstpage_image] =>[orig_patent_app_number] => 10865153 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865153
Method for fabricating a self-aligned bipolar transistor having recessed spacers Jun 8, 2004 Issued
Array ( [id] => 7795803 [patent_doc_number] => 08124509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Method of forming porous diamond films for semiconductor applications' [patent_app_type] => utility [patent_app_number] => 10/857057 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1827 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/124/08124509.pdf [firstpage_image] =>[orig_patent_app_number] => 10857057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857057
Method of forming porous diamond films for semiconductor applications May 27, 2004 Issued
Array ( [id] => 7206011 [patent_doc_number] => 20050258451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions' [patent_app_type] => utility [patent_app_number] => 10/849617 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8077 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258451.pdf [firstpage_image] =>[orig_patent_app_number] => 10849617 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849617
Methods of fabricating nitride-based transistors having regrown ohmic contact regions May 19, 2004 Issued
Array ( [id] => 7214067 [patent_doc_number] => 20050253194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'SOI-like structure in a bulk semiconductor substrate and method of forming same' [patent_app_type] => utility [patent_app_number] => 10/847607 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3425 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253194.pdf [firstpage_image] =>[orig_patent_app_number] => 10847607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847607
Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration May 16, 2004 Issued
Array ( [id] => 935367 [patent_doc_number] => 06974716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method for fabricating a titanium nitride sensing membrane on an EGFET' [patent_app_type] => utility [patent_app_number] => 10/802907 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3021 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974716.pdf [firstpage_image] =>[orig_patent_app_number] => 10802907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802907
Method for fabricating a titanium nitride sensing membrane on an EGFET Mar 16, 2004 Issued
Array ( [id] => 641787 [patent_doc_number] => 07122487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method for forming an oxide with improved oxygen bonding' [patent_app_type] => utility [patent_app_number] => 10/801377 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5526 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122487.pdf [firstpage_image] =>[orig_patent_app_number] => 10801377 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801377
Method for forming an oxide with improved oxygen bonding Mar 14, 2004 Issued
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