
Khanh B. Duong
Examiner (ID: 11457)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 696 |
| Issued Applications | 594 |
| Pending Applications | 7 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7127479
[patent_doc_number] => 20050059223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'Laser-irradiated thin films having variable thickness'
[patent_app_type] => utility
[patent_app_number] => 10/754157
[patent_app_country] => US
[patent_app_date] => 2004-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8968
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20050059223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10754157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754157 | Laser-irradiated thin films having variable thickness | Jan 8, 2004 | Issued |
Array
(
[id] => 509785
[patent_doc_number] => 07195988
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Semiconductor wafer and method of manufacturing a semiconductor device using a separation portion on a peripheral area of the semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 10/751657
[patent_app_country] => US
[patent_app_date] => 2004-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 44
[patent_no_of_words] => 5769
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/195/07195988.pdf
[firstpage_image] =>[orig_patent_app_number] => 10751657
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/751657 | Semiconductor wafer and method of manufacturing a semiconductor device using a separation portion on a peripheral area of the semiconductor wafer | Jan 5, 2004 | Issued |
Array
(
[id] => 7318373
[patent_doc_number] => 20040134899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Ceramic substrate for a semiconductor-production/inspection device'
[patent_app_type] => new
[patent_app_number] => 10/746081
[patent_app_country] => US
[patent_app_date] => 2003-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14854
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20040134899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746081
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746081 | Ceramic substrate for a semiconductor-production/inspection device | Dec 28, 2003 | Abandoned |
Array
(
[id] => 7335516
[patent_doc_number] => 20040132265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Separating method'
[patent_app_type] => new
[patent_app_number] => 10/740437
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 9616
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20040132265.pdf
[firstpage_image] =>[orig_patent_app_number] => 10740437
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/740437 | Method of separating a release layer from a substrate comprising hydrogen diffusion | Dec 21, 2003 | Issued |
Array
(
[id] => 7443287
[patent_doc_number] => 20040185681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Novel polysilicon material and semiconductor devices formed therefrom'
[patent_app_type] => new
[patent_app_number] => 10/740537
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3608
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20040185681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10740537
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/740537 | Polysilicon material and semiconductor devices formed therefrom | Dec 21, 2003 | Issued |
Array
(
[id] => 6996912
[patent_doc_number] => 20050136690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Defect control in gate dielectrics'
[patent_app_type] => utility
[patent_app_number] => 10/739617
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1860
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20050136690.pdf
[firstpage_image] =>[orig_patent_app_number] => 10739617
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/739617 | Method for controlling defects in gate dielectrics | Dec 17, 2003 | Issued |
Array
(
[id] => 1002369
[patent_doc_number] => 06908823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-21
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/737987
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2382
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/908/06908823.pdf
[firstpage_image] =>[orig_patent_app_number] => 10737987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/737987 | Method of manufacturing a semiconductor device | Dec 17, 2003 | Issued |
Array
(
[id] => 668433
[patent_doc_number] => 07094674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Method for production of contacts on a wafer'
[patent_app_type] => utility
[patent_app_number] => 10/739477
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2278
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/094/07094674.pdf
[firstpage_image] =>[orig_patent_app_number] => 10739477
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/739477 | Method for production of contacts on a wafer | Dec 17, 2003 | Issued |
Array
(
[id] => 6996854
[patent_doc_number] => 20050136632
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Implementation of split gate transistor technology with high-k gate dielectrics'
[patent_app_type] => utility
[patent_app_number] => 10/738957
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7967
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20050136632.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738957
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738957 | Method for fabricating split gate transistor device having high-k dielectrics | Dec 16, 2003 | Issued |
Array
(
[id] => 766367
[patent_doc_number] => 07008878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-07
[patent_title] => 'Plasma treatment and etching process for ultra-thin dielectric films'
[patent_app_type] => utility
[patent_app_number] => 10/738237
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 2942
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/008/07008878.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738237 | Plasma treatment and etching process for ultra-thin dielectric films | Dec 16, 2003 | Issued |
Array
(
[id] => 7287223
[patent_doc_number] => 20040147059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Method for manufacturing CMOS image sensor having microlens therein with high photosensitivity'
[patent_app_type] => new
[patent_app_number] => 10/737227
[patent_app_country] => US
[patent_app_date] => 2003-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5055
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20040147059.pdf
[firstpage_image] =>[orig_patent_app_number] => 10737227
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/737227 | Method for manufacturing CMOS image sensor having microlens therein with high photosensitivity | Dec 15, 2003 | Issued |
Array
(
[id] => 719886
[patent_doc_number] => 07049196
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-23
[patent_title] => 'Vertical gain cell and array for a dynamic random access memory and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 10/738449
[patent_app_country] => US
[patent_app_date] => 2003-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6222
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/049/07049196.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738449
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738449 | Vertical gain cell and array for a dynamic random access memory and method for forming the same | Dec 15, 2003 | Issued |
Array
(
[id] => 948809
[patent_doc_number] => 06962845
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-08
[patent_title] => 'Method for manufacturing semiconductor capacitor having double dielectric layer therein'
[patent_app_type] => utility
[patent_app_number] => 10/738177
[patent_app_country] => US
[patent_app_date] => 2003-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3556
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/962/06962845.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738177
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738177 | Method for manufacturing semiconductor capacitor having double dielectric layer therein | Dec 15, 2003 | Issued |
Array
(
[id] => 7097975
[patent_doc_number] => 20050130434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Method of surface pretreatment before selective epitaxial growth'
[patent_app_type] => utility
[patent_app_number] => 10/734197
[patent_app_country] => US
[patent_app_date] => 2003-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2167
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20050130434.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734197
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734197 | Method of surface pretreatment before selective epitaxial growth | Dec 14, 2003 | Abandoned |
Array
(
[id] => 700143
[patent_doc_number] => 07067855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Semiconductor structure having an abrupt doping profile'
[patent_app_type] => utility
[patent_app_number] => 10/735167
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4389
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10735167
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735167 | Semiconductor structure having an abrupt doping profile | Dec 11, 2003 | Issued |
Array
(
[id] => 7675164
[patent_doc_number] => 20040126954
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Deposition methods with time spaced and time abutting precursor pulses'
[patent_app_type] => new
[patent_app_number] => 10/734999
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3795
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20040126954.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734999
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734999 | Deposition methods with time spaced and time abutting precursor pulses | Dec 11, 2003 | Issued |
Array
(
[id] => 7289839
[patent_doc_number] => 20040110373
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Completely enclosed copper structure to avoid copper damage for damascene processes'
[patent_app_type] => new
[patent_app_number] => 10/726104
[patent_app_country] => US
[patent_app_date] => 2003-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1564
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20040110373.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726104
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726104 | Completely enclosed copper structure to avoid copper damage for damascene processes | Dec 1, 2003 | Abandoned |
Array
(
[id] => 785232
[patent_doc_number] => 06989319
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-01-24
[patent_title] => 'Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/718707
[patent_app_country] => US
[patent_app_date] => 2003-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 5305
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/989/06989319.pdf
[firstpage_image] =>[orig_patent_app_number] => 10718707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718707 | Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices | Nov 23, 2003 | Issued |
Array
(
[id] => 7409059
[patent_doc_number] => 20040106291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-03
[patent_title] => 'Thermally enhanced wafer-level chip scale package and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/719912
[patent_app_country] => US
[patent_app_date] => 2003-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2023
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20040106291.pdf
[firstpage_image] =>[orig_patent_app_number] => 10719912
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/719912 | Thermally enhanced wafer-level chip scale package and method of fabricating the same | Nov 20, 2003 | Abandoned |
Array
(
[id] => 448534
[patent_doc_number] => 07250342
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Method of fabricating a MOSFET having a recessed channel'
[patent_app_type] => utility
[patent_app_number] => 10/699047
[patent_app_country] => US
[patent_app_date] => 2003-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2902
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/250/07250342.pdf
[firstpage_image] =>[orig_patent_app_number] => 10699047
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/699047 | Method of fabricating a MOSFET having a recessed channel | Oct 29, 2003 | Issued |