Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 715556 [patent_doc_number] => 07052983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads' [patent_app_type] => utility [patent_app_number] => 10/688017 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 6396 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052983.pdf [firstpage_image] =>[orig_patent_app_number] => 10688017 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688017
Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads Oct 15, 2003 Issued
Array ( [id] => 7365317 [patent_doc_number] => 20040092107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions' [patent_app_type] => new [patent_app_number] => 10/686333 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5197 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092107.pdf [firstpage_image] =>[orig_patent_app_number] => 10686333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686333
Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions Oct 13, 2003 Issued
Array ( [id] => 7114312 [patent_doc_number] => 20050067612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Current controlling device' [patent_app_type] => utility [patent_app_number] => 10/675417 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20050067612.pdf [firstpage_image] =>[orig_patent_app_number] => 10675417 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675417
Method of forming a current controlling device Sep 29, 2003 Issued
Array ( [id] => 6905719 [patent_doc_number] => 20050101114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Triple damascene fuse' [patent_app_type] => utility [patent_app_number] => 10/675177 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3828 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101114.pdf [firstpage_image] =>[orig_patent_app_number] => 10675177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675177
Method for fabricating a triple damascene fuse Sep 29, 2003 Issued
Array ( [id] => 1046771 [patent_doc_number] => 06864166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Method of manufacturing wire bonded microelectronic device assemblies' [patent_app_type] => utility [patent_app_number] => 10/674869 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4665 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864166.pdf [firstpage_image] =>[orig_patent_app_number] => 10674869 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674869
Method of manufacturing wire bonded microelectronic device assemblies Sep 28, 2003 Issued
Array ( [id] => 1109070 [patent_doc_number] => 06809418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Integrated circuit package structure' [patent_app_type] => B1 [patent_app_number] => 10/660397 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1359 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809418.pdf [firstpage_image] =>[orig_patent_app_number] => 10660397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/660397
Integrated circuit package structure Sep 9, 2003 Issued
Array ( [id] => 938424 [patent_doc_number] => 06972253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Method for forming dielectric barrier layer in damascene structure' [patent_app_type] => utility [patent_app_number] => 10/657847 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6986 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972253.pdf [firstpage_image] =>[orig_patent_app_number] => 10657847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657847
Method for forming dielectric barrier layer in damascene structure Sep 8, 2003 Issued
Array ( [id] => 1095831 [patent_doc_number] => 06821803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of manufacturing an electroluminescence display device' [patent_app_type] => B2 [patent_app_number] => 10/642131 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3840 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821803.pdf [firstpage_image] =>[orig_patent_app_number] => 10642131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642131
Method of manufacturing an electroluminescence display device Aug 17, 2003 Issued
Array ( [id] => 630390 [patent_doc_number] => 07132350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Method for manufacturing a programmable eraseless memory' [patent_app_type] => utility [patent_app_number] => 10/641897 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 10009 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132350.pdf [firstpage_image] =>[orig_patent_app_number] => 10641897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641897
Method for manufacturing a programmable eraseless memory Aug 14, 2003 Issued
Array ( [id] => 7375782 [patent_doc_number] => 20040219747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'METHOD FOR FORMING VERTICAL TRANSISTOR AND TRENCH CAPACITOR' [patent_app_type] => new [patent_app_number] => 10/640097 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219747.pdf [firstpage_image] =>[orig_patent_app_number] => 10640097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640097
Method for forming vertical transistor and trench capacitor Aug 12, 2003 Issued
Array ( [id] => 961110 [patent_doc_number] => 06951823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Plasma ashing process' [patent_app_type] => utility [patent_app_number] => 10/638570 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7216 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951823.pdf [firstpage_image] =>[orig_patent_app_number] => 10638570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/638570
Plasma ashing process Aug 10, 2003 Issued
Array ( [id] => 7383253 [patent_doc_number] => 20040029308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method for manufacturing contact structures of wirings' [patent_app_type] => new [patent_app_number] => 10/634867 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8416 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029308.pdf [firstpage_image] =>[orig_patent_app_number] => 10634867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634867
Method for manufacturing contact structures of wirings Aug 5, 2003 Issued
Array ( [id] => 1009331 [patent_doc_number] => 06900093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method of fabricating a zener diode chip for use as a shunt in Christmas tree lighting' [patent_app_type] => utility [patent_app_number] => 10/633687 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900093.pdf [firstpage_image] =>[orig_patent_app_number] => 10633687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633687
Method of fabricating a zener diode chip for use as a shunt in Christmas tree lighting Aug 4, 2003 Issued
Array ( [id] => 7154786 [patent_doc_number] => 20050026408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Preventing silicide formation at the gate electrode in a replacement metal gate technology' [patent_app_type] => utility [patent_app_number] => 10/629127 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1356 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026408.pdf [firstpage_image] =>[orig_patent_app_number] => 10629127 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629127
Preventing silicide formation at the gate electrode in a replacement metal gate technology Jul 28, 2003 Issued
Array ( [id] => 7154759 [patent_doc_number] => 20050026397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'CRACK STOP FOR LOW K DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 10/604517 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1917 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026397.pdf [firstpage_image] =>[orig_patent_app_number] => 10604517 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604517
CRACK STOP FOR LOW K DIELECTRICS Jul 27, 2003 Abandoned
Array ( [id] => 7159507 [patent_doc_number] => 20040075149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs' [patent_app_type] => new [patent_app_number] => 10/625018 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5615 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075149.pdf [firstpage_image] =>[orig_patent_app_number] => 10625018 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625018
CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs Jul 22, 2003 Abandoned
Array ( [id] => 285399 [patent_doc_number] => 07550325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Method of manufacturing an active matrix display device' [patent_app_type] => utility [patent_app_number] => 10/620565 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 9398 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/550/07550325.pdf [firstpage_image] =>[orig_patent_app_number] => 10620565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620565
Method of manufacturing an active matrix display device Jul 16, 2003 Issued
Array ( [id] => 7408830 [patent_doc_number] => 20040106259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'High coupling split-gate transistor' [patent_app_type] => new [patent_app_number] => 10/615874 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3030 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106259.pdf [firstpage_image] =>[orig_patent_app_number] => 10615874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615874
High coupling split-gate transistor Jul 9, 2003 Abandoned
Array ( [id] => 701553 [patent_doc_number] => 07064063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Photo-thermal induced diffusion' [patent_app_type] => utility [patent_app_number] => 10/617107 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064063.pdf [firstpage_image] =>[orig_patent_app_number] => 10617107 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617107
Photo-thermal induced diffusion Jul 8, 2003 Issued
Array ( [id] => 1111097 [patent_doc_number] => 06806204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Semiconductor etch speed modification' [patent_app_type] => B1 [patent_app_number] => 10/611837 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7972 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806204.pdf [firstpage_image] =>[orig_patent_app_number] => 10611837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611837
Semiconductor etch speed modification Jun 29, 2003 Issued
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