
Khanh B. Duong
Examiner (ID: 11457)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 696 |
| Issued Applications | 594 |
| Pending Applications | 7 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 715556
[patent_doc_number] => 07052983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-30
[patent_title] => 'Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads'
[patent_app_type] => utility
[patent_app_number] => 10/688017
[patent_app_country] => US
[patent_app_date] => 2003-10-16
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[pdf_file] => patents/07/052/07052983.pdf
[firstpage_image] =>[orig_patent_app_number] => 10688017
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/688017 | Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads | Oct 15, 2003 | Issued |
Array
(
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[patent_doc_number] => 20040092107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions'
[patent_app_type] => new
[patent_app_number] => 10/686333
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[patent_app_date] => 2003-10-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/686333 | Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions | Oct 13, 2003 | Issued |
Array
(
[id] => 7114312
[patent_doc_number] => 20050067612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Current controlling device'
[patent_app_type] => utility
[patent_app_number] => 10/675417
[patent_app_country] => US
[patent_app_date] => 2003-09-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/675417 | Method of forming a current controlling device | Sep 29, 2003 | Issued |
Array
(
[id] => 6905719
[patent_doc_number] => 20050101114
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Triple damascene fuse'
[patent_app_type] => utility
[patent_app_number] => 10/675177
[patent_app_country] => US
[patent_app_date] => 2003-09-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/675177 | Method for fabricating a triple damascene fuse | Sep 29, 2003 | Issued |
Array
(
[id] => 1046771
[patent_doc_number] => 06864166
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[patent_kind] => B1
[patent_issue_date] => 2005-03-08
[patent_title] => 'Method of manufacturing wire bonded microelectronic device assemblies'
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[patent_app_country] => US
[patent_app_date] => 2003-09-29
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[pdf_file] => patents/06/864/06864166.pdf
[firstpage_image] =>[orig_patent_app_number] => 10674869
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/674869 | Method of manufacturing wire bonded microelectronic device assemblies | Sep 28, 2003 | Issued |
Array
(
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[patent_issue_date] => 2004-10-26
[patent_title] => 'Integrated circuit package structure'
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[patent_app_number] => 10/660397
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Array
(
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[patent_issue_date] => 2005-12-06
[patent_title] => 'Method for forming dielectric barrier layer in damascene structure'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657847 | Method for forming dielectric barrier layer in damascene structure | Sep 8, 2003 | Issued |
Array
(
[id] => 1095831
[patent_doc_number] => 06821803
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[patent_issue_date] => 2004-11-23
[patent_title] => 'Method of manufacturing an electroluminescence display device'
[patent_app_type] => B2
[patent_app_number] => 10/642131
[patent_app_country] => US
[patent_app_date] => 2003-08-18
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[pdf_file] => patents/06/821/06821803.pdf
[firstpage_image] =>[orig_patent_app_number] => 10642131
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/642131 | Method of manufacturing an electroluminescence display device | Aug 17, 2003 | Issued |
Array
(
[id] => 630390
[patent_doc_number] => 07132350
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Method for manufacturing a programmable eraseless memory'
[patent_app_type] => utility
[patent_app_number] => 10/641897
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10641897
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/641897 | Method for manufacturing a programmable eraseless memory | Aug 14, 2003 | Issued |
Array
(
[id] => 7375782
[patent_doc_number] => 20040219747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'METHOD FOR FORMING VERTICAL TRANSISTOR AND TRENCH CAPACITOR'
[patent_app_type] => new
[patent_app_number] => 10/640097
[patent_app_country] => US
[patent_app_date] => 2003-08-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0219/20040219747.pdf
[firstpage_image] =>[orig_patent_app_number] => 10640097
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640097 | Method for forming vertical transistor and trench capacitor | Aug 12, 2003 | Issued |
Array
(
[id] => 961110
[patent_doc_number] => 06951823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-04
[patent_title] => 'Plasma ashing process'
[patent_app_type] => utility
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[pdf_file] => patents/06/951/06951823.pdf
[firstpage_image] =>[orig_patent_app_number] => 10638570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/638570 | Plasma ashing process | Aug 10, 2003 | Issued |
Array
(
[id] => 7383253
[patent_doc_number] => 20040029308
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[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Method for manufacturing contact structures of wirings'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/634867 | Method for manufacturing contact structures of wirings | Aug 5, 2003 | Issued |
Array
(
[id] => 1009331
[patent_doc_number] => 06900093
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Method of fabricating a zener diode chip for use as a shunt in Christmas tree lighting'
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[patent_app_number] => 10/633687
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/633687 | Method of fabricating a zener diode chip for use as a shunt in Christmas tree lighting | Aug 4, 2003 | Issued |
Array
(
[id] => 7154786
[patent_doc_number] => 20050026408
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[patent_title] => 'Preventing silicide formation at the gate electrode in a replacement metal gate technology'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/629127 | Preventing silicide formation at the gate electrode in a replacement metal gate technology | Jul 28, 2003 | Issued |
Array
(
[id] => 7154759
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[patent_issue_date] => 2005-02-03
[patent_title] => 'CRACK STOP FOR LOW K DIELECTRICS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604517 | CRACK STOP FOR LOW K DIELECTRICS | Jul 27, 2003 | Abandoned |
Array
(
[id] => 7159507
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[patent_title] => 'CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/625018 | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs | Jul 22, 2003 | Abandoned |
Array
(
[id] => 285399
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[patent_issue_date] => 2009-06-23
[patent_title] => 'Method of manufacturing an active matrix display device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620565 | Method of manufacturing an active matrix display device | Jul 16, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/615874 | High coupling split-gate transistor | Jul 9, 2003 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617107 | Photo-thermal induced diffusion | Jul 8, 2003 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 10611837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/611837 | Semiconductor etch speed modification | Jun 29, 2003 | Issued |