Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7061231 [patent_doc_number] => 20050003592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'All-around MOSFET gate and methods of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 10/465087 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5033 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003592.pdf [firstpage_image] =>[orig_patent_app_number] => 10465087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/465087
All-around MOSFET gate and methods of manufacture thereof Jun 17, 2003 Abandoned
Array ( [id] => 7325232 [patent_doc_number] => 20040252559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Transplanted magnetic random access memory (MRAM) devices on thermally-sensitive substrates using laser transfer and method for making the same' [patent_app_type] => new [patent_app_number] => 10/459517 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2446 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252559.pdf [firstpage_image] =>[orig_patent_app_number] => 10459517 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459517
Method of forming magnetic random access memory (MRAM) devices on thermally-sensitive substrates using laser transfer Jun 11, 2003 Issued
Array ( [id] => 623594 [patent_doc_number] => 07138318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate' [patent_app_type] => utility [patent_app_number] => 10/447047 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2718 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138318.pdf [firstpage_image] =>[orig_patent_app_number] => 10447047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447047
Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate May 27, 2003 Issued
Array ( [id] => 6662113 [patent_doc_number] => 20030201439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/446187 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18330 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20030201439.pdf [firstpage_image] =>[orig_patent_app_number] => 10446187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446187
Semiconductor device having thin film transistor and light-shielding film May 27, 2003 Issued
Array ( [id] => 6610621 [patent_doc_number] => 20030209716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Semiconductor laser element having excellent light confinement effect and method for producing the semiconductor laser element' [patent_app_type] => new [patent_app_number] => 10/442377 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11029 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20030209716.pdf [firstpage_image] =>[orig_patent_app_number] => 10442377 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442377
Semiconductor laser element having excellent light confinement effect and method for producing the semiconductor laser element May 20, 2003 Abandoned
Array ( [id] => 6711192 [patent_doc_number] => 20030170941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'METHOD FOR LOW TOPOGRAPHY SEMICONDUCTOR DEVICE FORMATION' [patent_app_type] => new [patent_app_number] => 10/249917 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2381 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20030170941.pdf [firstpage_image] =>[orig_patent_app_number] => 10249917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249917
Method for low topography semiconductor device formation May 18, 2003 Issued
Array ( [id] => 1031053 [patent_doc_number] => 06878605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate' [patent_app_type] => utility [patent_app_number] => 10/441527 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3283 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878605.pdf [firstpage_image] =>[orig_patent_app_number] => 10441527 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441527
Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate May 18, 2003 Issued
Array ( [id] => 345450 [patent_doc_number] => 07498640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby' [patent_app_type] => utility [patent_app_number] => 10/437930 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4732 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498640.pdf [firstpage_image] =>[orig_patent_app_number] => 10437930 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437930
Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby May 14, 2003 Issued
Array ( [id] => 1104728 [patent_doc_number] => 06812052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method for fabricating low-temperature polysilicon organic electroluminescent device' [patent_app_type] => B2 [patent_app_number] => 10/427957 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3765 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812052.pdf [firstpage_image] =>[orig_patent_app_number] => 10427957 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427957
Method for fabricating low-temperature polysilicon organic electroluminescent device May 1, 2003 Issued
Array ( [id] => 7375866 [patent_doc_number] => 20040219764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Vacuum package fabrication of integrated circuit components' [patent_app_type] => new [patent_app_number] => 10/428627 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3298 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219764.pdf [firstpage_image] =>[orig_patent_app_number] => 10428627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428627
Vacuum package fabrication of integrated circuit components May 1, 2003 Issued
Array ( [id] => 7359697 [patent_doc_number] => 20040014260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Copper fuse structure and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/426787 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014260.pdf [firstpage_image] =>[orig_patent_app_number] => 10426787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426787
Method for manufacturing a copper fuse structure Apr 30, 2003 Issued
Array ( [id] => 7135113 [patent_doc_number] => 20040043563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'METHOD FOR FABRICATING A SPLIT GATE FLASH MEMORY CELL' [patent_app_type] => new [patent_app_number] => 10/426347 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2872 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043563.pdf [firstpage_image] =>[orig_patent_app_number] => 10426347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426347
Method for fabricating a split gate flash memory cell Apr 29, 2003 Issued
Array ( [id] => 1082890 [patent_doc_number] => 06833311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Manufacturing method for a shallow trench isolation region with high aspect ratio' [patent_app_type] => B2 [patent_app_number] => 10/426327 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2208 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833311.pdf [firstpage_image] =>[orig_patent_app_number] => 10426327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426327
Manufacturing method for a shallow trench isolation region with high aspect ratio Apr 29, 2003 Issued
Array ( [id] => 698845 [patent_doc_number] => 07067356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method of fabricating microelectronic package having a bumpless laminated interconnection layer' [patent_app_type] => utility [patent_app_number] => 10/424383 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 5094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067356.pdf [firstpage_image] =>[orig_patent_app_number] => 10424383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424383
Method of fabricating microelectronic package having a bumpless laminated interconnection layer Apr 27, 2003 Issued
Array ( [id] => 1168724 [patent_doc_number] => 06753237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method of shallow trench isolation fill-in without generation of void' [patent_app_type] => B1 [patent_app_number] => 10/424657 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 2625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753237.pdf [firstpage_image] =>[orig_patent_app_number] => 10424657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424657
Method of shallow trench isolation fill-in without generation of void Apr 27, 2003 Issued
Array ( [id] => 1126399 [patent_doc_number] => 06790693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method for fabricating a laser diode using a reflective layer including an air layer' [patent_app_type] => B2 [patent_app_number] => 10/420704 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3203 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790693.pdf [firstpage_image] =>[orig_patent_app_number] => 10420704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420704
Method for fabricating a laser diode using a reflective layer including an air layer Apr 22, 2003 Issued
Array ( [id] => 1126478 [patent_doc_number] => 06790708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Encapsulation process using a partial slot cover and a package formed by the process' [patent_app_type] => B2 [patent_app_number] => 10/421137 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790708.pdf [firstpage_image] =>[orig_patent_app_number] => 10421137 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421137
Encapsulation process using a partial slot cover and a package formed by the process Apr 22, 2003 Issued
Array ( [id] => 6635724 [patent_doc_number] => 20030211646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Compositions and devices made by synthesis of layers, coatings or films using electrostatic fields' [patent_app_type] => new [patent_app_number] => 10/420087 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13688 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211646.pdf [firstpage_image] =>[orig_patent_app_number] => 10420087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420087
Compositions and devices made by synthesis of layers, coatings or films using electrostatic fields Apr 21, 2003 Abandoned
Array ( [id] => 303532 [patent_doc_number] => 07534668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Method of fabricating etch-stopped SOI back-gate contact' [patent_app_type] => utility [patent_app_number] => 10/417627 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2555 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534668.pdf [firstpage_image] =>[orig_patent_app_number] => 10417627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417627
Method of fabricating etch-stopped SOI back-gate contact Apr 16, 2003 Issued
Array ( [id] => 7429345 [patent_doc_number] => 20040209458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Semiconductor device having rounding profile structure for reducing step profile and manufacturing processing stress and its manufacturing method' [patent_app_type] => new [patent_app_number] => 10/414087 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3341 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209458.pdf [firstpage_image] =>[orig_patent_app_number] => 10414087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414087
Semiconductor device having rounding profile structure for reducing step profile and manufacturing processing stress and its manufacturing method Apr 15, 2003 Abandoned
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