Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 448499 [patent_doc_number] => 07250333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method of fabricating a linearized output driver and terminator' [patent_app_type] => utility [patent_app_number] => 10/394977 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3863 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250333.pdf [firstpage_image] =>[orig_patent_app_number] => 10394977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394977
Method of fabricating a linearized output driver and terminator Mar 19, 2003 Issued
Array ( [id] => 708639 [patent_doc_number] => 07061050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Semiconductor device utilizing both fully and partially depleted devices' [patent_app_type] => utility [patent_app_number] => 10/487157 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061050.pdf [firstpage_image] =>[orig_patent_app_number] => 10487157 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/487157
Semiconductor device utilizing both fully and partially depleted devices Mar 16, 2003 Issued
Array ( [id] => 6847151 [patent_doc_number] => 20030166318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Atomic layer deposition of capacitor dielectric' [patent_app_type] => new [patent_app_number] => 10/385029 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2338 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166318.pdf [firstpage_image] =>[orig_patent_app_number] => 10385029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/385029
Atomic layer deposition of capacitor dielectric Mar 9, 2003 Abandoned
Array ( [id] => 1104884 [patent_doc_number] => 06812107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method for improved alignment tolerance in a bipolar transistor' [patent_app_type] => B1 [patent_app_number] => 10/375727 [patent_app_country] => US [patent_app_date] => 2003-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5072 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812107.pdf [firstpage_image] =>[orig_patent_app_number] => 10375727 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375727
Method for improved alignment tolerance in a bipolar transistor Feb 25, 2003 Issued
Array ( [id] => 7465470 [patent_doc_number] => 20040166641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'METHOD OF MANUFACTURING HIGH COUPLING RATIO FLASH MEMORY HAVING SIDEWALL SPACER FLOATING GATE ELECTRODE' [patent_app_type] => new [patent_app_number] => 10/248867 [patent_app_country] => US [patent_app_date] => 2003-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166641.pdf [firstpage_image] =>[orig_patent_app_number] => 10248867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248867
Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode Feb 25, 2003 Issued
Array ( [id] => 6829965 [patent_doc_number] => 20030181023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method of processing silicon single crystal ingot' [patent_app_type] => new [patent_app_number] => 10/362947 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3189 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20030181023.pdf [firstpage_image] =>[orig_patent_app_number] => 10362947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362947
Method of processing silicon single crystal ingot Feb 24, 2003 Abandoned
Array ( [id] => 773505 [patent_doc_number] => 07001831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method for depositing a film on a substrate using Cat-PACVD' [patent_app_type] => utility [patent_app_number] => 10/371217 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8480 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/001/07001831.pdf [firstpage_image] =>[orig_patent_app_number] => 10371217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/371217
Method for depositing a film on a substrate using Cat-PACVD Feb 19, 2003 Issued
Array ( [id] => 1253240 [patent_doc_number] => 06670205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method of fabricating image sensor equipped with lens' [patent_app_type] => B1 [patent_app_number] => 10/365987 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1902 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670205.pdf [firstpage_image] =>[orig_patent_app_number] => 10365987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/365987
Method of fabricating image sensor equipped with lens Feb 12, 2003 Issued
Array ( [id] => 1273916 [patent_doc_number] => 06649489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Poly etching solution to improve silicon trench for low STI profile' [patent_app_type] => B1 [patent_app_number] => 10/366207 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3796 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649489.pdf [firstpage_image] =>[orig_patent_app_number] => 10366207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366207
Poly etching solution to improve silicon trench for low STI profile Feb 12, 2003 Issued
Array ( [id] => 6832106 [patent_doc_number] => 20030159651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Thin film structure, device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/365537 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8571 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159651.pdf [firstpage_image] =>[orig_patent_app_number] => 10365537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/365537
Thin-film coating apparatus Feb 12, 2003 Issued
Array ( [id] => 390626 [patent_doc_number] => 07301222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages' [patent_app_type] => utility [patent_app_number] => 10/366067 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3697 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301222.pdf [firstpage_image] =>[orig_patent_app_number] => 10366067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366067
Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages Feb 11, 2003 Issued
Array ( [id] => 7447732 [patent_doc_number] => 20040164320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Method of activating polysilicon gate structure dopants after offset spacer deposition' [patent_app_type] => new [patent_app_number] => 10/361877 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2449 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164320.pdf [firstpage_image] =>[orig_patent_app_number] => 10361877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361877
Method of activating polysilicon gate structure dopants after offset spacer deposition Feb 9, 2003 Issued
Array ( [id] => 6787749 [patent_doc_number] => 20030138988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method of manufacturing a solid-state imaging device' [patent_app_type] => new [patent_app_number] => 10/358142 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20030138988.pdf [firstpage_image] =>[orig_patent_app_number] => 10358142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358142
Method of manufacturing a solid-state imaging device Feb 4, 2003 Issued
Array ( [id] => 1071847 [patent_doc_number] => 06841431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method for reducing the contact resistance' [patent_app_type] => utility [patent_app_number] => 10/352937 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2674 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841431.pdf [firstpage_image] =>[orig_patent_app_number] => 10352937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352937
Method for reducing the contact resistance Jan 28, 2003 Issued
Array ( [id] => 1089138 [patent_doc_number] => 06828207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method of Fabricating a capacitor structure having hemispherical grains' [patent_app_type] => B2 [patent_app_number] => 10/352947 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1330 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828207.pdf [firstpage_image] =>[orig_patent_app_number] => 10352947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352947
Method of Fabricating a capacitor structure having hemispherical grains Jan 28, 2003 Issued
Array ( [id] => 6843205 [patent_doc_number] => 20030148552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Semiconductor structures with cavities, and methods of fabrication' [patent_app_type] => new [patent_app_number] => 10/352607 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4408 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148552.pdf [firstpage_image] =>[orig_patent_app_number] => 10352607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352607
Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity Jan 26, 2003 Issued
Array ( [id] => 7287235 [patent_doc_number] => 20040147070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Ultra-shallow junction formation for nano MOS devices using amorphous-si capping layer' [patent_app_type] => new [patent_app_number] => 10/349967 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6968 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147070.pdf [firstpage_image] =>[orig_patent_app_number] => 10349967 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349967
Ultra-shallow junction formation for nano MOS devices using amorphous-si capping layer Jan 23, 2003 Abandoned
Array ( [id] => 1111061 [patent_doc_number] => 06806192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method of barrier-less integration with copper alloy' [patent_app_type] => B2 [patent_app_number] => 10/350837 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3569 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806192.pdf [firstpage_image] =>[orig_patent_app_number] => 10350837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/350837
Method of barrier-less integration with copper alloy Jan 23, 2003 Issued
Array ( [id] => 1202709 [patent_doc_number] => 06720246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Flip chip assembly process for forming an underfill encapsulant' [patent_app_type] => B1 [patent_app_number] => 10/348957 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2180 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720246.pdf [firstpage_image] =>[orig_patent_app_number] => 10348957 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348957
Flip chip assembly process for forming an underfill encapsulant Jan 22, 2003 Issued
Array ( [id] => 7677587 [patent_doc_number] => 20040152239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Interface improvement by electron beam process' [patent_app_type] => new [patent_app_number] => 10/348447 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4500 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152239.pdf [firstpage_image] =>[orig_patent_app_number] => 10348447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348447
Interface improvement by electron beam process Jan 20, 2003 Abandoned
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