
Khanh B. Duong
Examiner (ID: 11457)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 696 |
| Issued Applications | 594 |
| Pending Applications | 7 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 448499
[patent_doc_number] => 07250333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Method of fabricating a linearized output driver and terminator'
[patent_app_type] => utility
[patent_app_number] => 10/394977
[patent_app_country] => US
[patent_app_date] => 2003-03-20
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/250/07250333.pdf
[firstpage_image] =>[orig_patent_app_number] => 10394977
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/394977 | Method of fabricating a linearized output driver and terminator | Mar 19, 2003 | Issued |
Array
(
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[patent_doc_number] => 07061050
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[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Semiconductor device utilizing both fully and partially depleted devices'
[patent_app_type] => utility
[patent_app_number] => 10/487157
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[patent_app_date] => 2003-03-17
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[firstpage_image] =>[orig_patent_app_number] => 10487157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/487157 | Semiconductor device utilizing both fully and partially depleted devices | Mar 16, 2003 | Issued |
Array
(
[id] => 6847151
[patent_doc_number] => 20030166318
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[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'Atomic layer deposition of capacitor dielectric'
[patent_app_type] => new
[patent_app_number] => 10/385029
[patent_app_country] => US
[patent_app_date] => 2003-03-10
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[firstpage_image] =>[orig_patent_app_number] => 10385029
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385029 | Atomic layer deposition of capacitor dielectric | Mar 9, 2003 | Abandoned |
Array
(
[id] => 1104884
[patent_doc_number] => 06812107
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[patent_kind] => B1
[patent_issue_date] => 2004-11-02
[patent_title] => 'Method for improved alignment tolerance in a bipolar transistor'
[patent_app_type] => B1
[patent_app_number] => 10/375727
[patent_app_country] => US
[patent_app_date] => 2003-02-26
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[firstpage_image] =>[orig_patent_app_number] => 10375727
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/375727 | Method for improved alignment tolerance in a bipolar transistor | Feb 25, 2003 | Issued |
Array
(
[id] => 7465470
[patent_doc_number] => 20040166641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'METHOD OF MANUFACTURING HIGH COUPLING RATIO FLASH MEMORY HAVING SIDEWALL SPACER FLOATING GATE ELECTRODE'
[patent_app_type] => new
[patent_app_number] => 10/248867
[patent_app_country] => US
[patent_app_date] => 2003-02-26
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[pdf_file] => publications/A1/0166/20040166641.pdf
[firstpage_image] =>[orig_patent_app_number] => 10248867
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248867 | Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode | Feb 25, 2003 | Issued |
Array
(
[id] => 6829965
[patent_doc_number] => 20030181023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Method of processing silicon single crystal ingot'
[patent_app_type] => new
[patent_app_number] => 10/362947
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[firstpage_image] =>[orig_patent_app_number] => 10362947
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/362947 | Method of processing silicon single crystal ingot | Feb 24, 2003 | Abandoned |
Array
(
[id] => 773505
[patent_doc_number] => 07001831
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[patent_issue_date] => 2006-02-21
[patent_title] => 'Method for depositing a film on a substrate using Cat-PACVD'
[patent_app_type] => utility
[patent_app_number] => 10/371217
[patent_app_country] => US
[patent_app_date] => 2003-02-20
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[pdf_file] => patents/07/001/07001831.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/371217 | Method for depositing a film on a substrate using Cat-PACVD | Feb 19, 2003 | Issued |
Array
(
[id] => 1253240
[patent_doc_number] => 06670205
[patent_country] => US
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[patent_issue_date] => 2003-12-30
[patent_title] => 'Method of fabricating image sensor equipped with lens'
[patent_app_type] => B1
[patent_app_number] => 10/365987
[patent_app_country] => US
[patent_app_date] => 2003-02-13
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[firstpage_image] =>[orig_patent_app_number] => 10365987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/365987 | Method of fabricating image sensor equipped with lens | Feb 12, 2003 | Issued |
Array
(
[id] => 1273916
[patent_doc_number] => 06649489
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[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Poly etching solution to improve silicon trench for low STI profile'
[patent_app_type] => B1
[patent_app_number] => 10/366207
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/366207 | Poly etching solution to improve silicon trench for low STI profile | Feb 12, 2003 | Issued |
Array
(
[id] => 6832106
[patent_doc_number] => 20030159651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Thin film structure, device and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/365537
[patent_app_country] => US
[patent_app_date] => 2003-02-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/365537 | Thin-film coating apparatus | Feb 12, 2003 | Issued |
Array
(
[id] => 390626
[patent_doc_number] => 07301222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-11-27
[patent_title] => 'Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages'
[patent_app_type] => utility
[patent_app_number] => 10/366067
[patent_app_country] => US
[patent_app_date] => 2003-02-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/366067 | Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages | Feb 11, 2003 | Issued |
Array
(
[id] => 7447732
[patent_doc_number] => 20040164320
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[patent_issue_date] => 2004-08-26
[patent_title] => 'Method of activating polysilicon gate structure dopants after offset spacer deposition'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361877 | Method of activating polysilicon gate structure dopants after offset spacer deposition | Feb 9, 2003 | Issued |
Array
(
[id] => 6787749
[patent_doc_number] => 20030138988
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[patent_title] => 'Method of manufacturing a solid-state imaging device'
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Array
(
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[patent_title] => 'Method for reducing the contact resistance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/352937 | Method for reducing the contact resistance | Jan 28, 2003 | Issued |
Array
(
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[patent_title] => 'Method of Fabricating a capacitor structure having hemispherical grains'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/352947 | Method of Fabricating a capacitor structure having hemispherical grains | Jan 28, 2003 | Issued |
Array
(
[id] => 6843205
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[patent_issue_date] => 2003-08-07
[patent_title] => 'Semiconductor structures with cavities, and methods of fabrication'
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[patent_app_number] => 10/352607
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/352607 | Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity | Jan 26, 2003 | Issued |
Array
(
[id] => 7287235
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[patent_title] => 'Ultra-shallow junction formation for nano MOS devices using amorphous-si capping layer'
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[patent_app_number] => 10/349967
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Array
(
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[patent_title] => 'Method of barrier-less integration with copper alloy'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/350837 | Method of barrier-less integration with copper alloy | Jan 23, 2003 | Issued |
Array
(
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[patent_title] => 'Flip chip assembly process for forming an underfill encapsulant'
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Array
(
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[patent_title] => 'Interface improvement by electron beam process'
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[firstpage_image] =>[orig_patent_app_number] => 10348447
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/348447 | Interface improvement by electron beam process | Jan 20, 2003 | Abandoned |