Khanh B. Duong

Array ( [id] => 7309211 [patent_doc_number] => 20040142517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Hatted polysilicon gate structure for improving salicide performance and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/347007 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2625 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142517.pdf [firstpage_image] =>[orig_patent_app_number] => 10347007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6851568 [patent_doc_number] => 20030143771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Method of fabricating nitride semiconductor, method of fabricating nitride semiconductor device, nitride semiconductor device, semiconductor light emitting device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/345377 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 25883 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20030143771.pdf [firstpage_image] =>[orig_patent_app_number] => 10345377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629849 [patent_doc_number] => 06818507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method of manufacturing semiconductor device including memory region and logic circuit region' [patent_app_type] => B2 [patent_app_number] => 10/342307 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 7797 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818507.pdf [firstpage_image] =>[orig_patent_app_number] => 10342307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149027 [patent_doc_number] => 06770495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method for revealing active regions in a SOI structure for DUT backside inspection' [patent_app_type] => B1 [patent_app_number] => 10/346507 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1212 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770495.pdf [firstpage_image] =>[orig_patent_app_number] => 10346507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6801274 [patent_doc_number] => 20030096439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Methods for forming index guided vertical cavity surface emitting lasers' [patent_app_type] => new [patent_app_number] => 10/339057 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4429 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096439.pdf [firstpage_image] =>[orig_patent_app_number] => 10339057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1056372 [patent_doc_number] => 06855595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Method for manufacturing a CMOS image sensor having a capacitor\'s top electrode in contact with a photo-sensing element' [patent_app_type] => utility [patent_app_number] => 10/326680 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 2803 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855595.pdf [firstpage_image] =>[orig_patent_app_number] => 10326680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1073639 [patent_doc_number] => 06838304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'MEMS element manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/468757 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 8014 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838304.pdf [firstpage_image] =>[orig_patent_app_number] => 10468757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6792133 [patent_doc_number] => 20030087477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Repairable flip clip semiconductor device with excellent packaging reliability and method of manufacturing same' [patent_app_type] => new [patent_app_number] => 10/317384 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3606 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20030087477.pdf [firstpage_image] =>[orig_patent_app_number] => 10317384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6813738 [patent_doc_number] => 20030073288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation' [patent_app_type] => new [patent_app_number] => 10/295738 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2342 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073288.pdf [firstpage_image] =>[orig_patent_app_number] => 10295738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6787767 [patent_doc_number] => 20030139006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method for producing capacitor structures' [patent_app_type] => new [patent_app_number] => 10/258927 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5267 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139006.pdf [firstpage_image] =>[orig_patent_app_number] => 10258927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6837189 [patent_doc_number] => 20030034529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs' [patent_app_type] => new [patent_app_number] => 10/266339 [patent_app_country] => US [patent_app_date] => 2002-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5612 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034529.pdf [firstpage_image] =>[orig_patent_app_number] => 10266339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7964337 [patent_doc_number] => 06680258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method of forming an opening through an insulating layer of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/261947 [patent_app_country] => US [patent_app_date] => 2002-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 2745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680258.pdf [firstpage_image] =>[orig_patent_app_number] => 10261947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1245681 [patent_doc_number] => 06677201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors' [patent_app_type] => B1 [patent_app_number] => 10/261407 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2129 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677201.pdf [firstpage_image] =>[orig_patent_app_number] => 10261407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1280819 [patent_doc_number] => 06642079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Process of fabricating flip chip interconnection structure' [patent_app_type] => B1 [patent_app_number] => 10/065297 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2979 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642079.pdf [firstpage_image] =>[orig_patent_app_number] => 10065297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1253390 [patent_doc_number] => 06670274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure' [patent_app_type] => B1 [patent_app_number] => 10/261967 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1532 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670274.pdf [firstpage_image] =>[orig_patent_app_number] => 10261967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6683381 [patent_doc_number] => 20030119245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Semiconductor device having a trench isolation and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/237022 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 21354 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119245.pdf [firstpage_image] =>[orig_patent_app_number] => 10237022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6811762 [patent_doc_number] => 20030071312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Thin film semiconductor device having a gate electrode insulator formed through high-heat oxidization' [patent_app_type] => new [patent_app_number] => 10/236537 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5850 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20030071312.pdf [firstpage_image] =>[orig_patent_app_number] => 10236537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6792138 [patent_doc_number] => 20030087482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Shallow trench contact structure to solve the problem or schottky diode leakage' [patent_app_type] => new [patent_app_number] => 10/236535 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20030087482.pdf [firstpage_image] =>[orig_patent_app_number] => 10236535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1152391 [patent_doc_number] => 06767836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method of cleaning a CVD reaction chamber using an active oxygen species' [patent_app_type] => B2 [patent_app_number] => 10/235217 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5261 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/767/06767836.pdf [firstpage_image] =>[orig_patent_app_number] => 10235217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1188846 [patent_doc_number] => 06734077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method for fabricating a trench capacitor for a semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/234547 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3924 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734077.pdf [firstpage_image] =>[orig_patent_app_number] => 10234547 [rel_patent_id] =>[rel_patent_doc_number] =>)