Search

Khanh B. Duong

Examiner (ID: 11457)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
696
Issued Applications
594
Pending Applications
7
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1396894 [patent_doc_number] => 06531376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method of making a semiconductor device with a low permittivity region' [patent_app_type] => B1 [patent_app_number] => 10/123657 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531376.pdf [firstpage_image] =>[orig_patent_app_number] => 10123657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/123657
Method of making a semiconductor device with a low permittivity region Apr 16, 2002 Issued
Array ( [id] => 1256199 [patent_doc_number] => 06667252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method of manufacturing compound semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/114057 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5254 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667252.pdf [firstpage_image] =>[orig_patent_app_number] => 10114057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/114057
Method of manufacturing compound semiconductor substrate Apr 2, 2002 Issued
Array ( [id] => 6649817 [patent_doc_number] => 20030104707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'System and method for improved thin dielectric films' [patent_app_type] => new [patent_app_number] => 10/106677 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6048 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104707.pdf [firstpage_image] =>[orig_patent_app_number] => 10106677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106677
System and method for improved thin dielectric films Mar 24, 2002 Abandoned
Array ( [id] => 6838906 [patent_doc_number] => 20030036246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Manufacturing method of semiconductor device having trench type element isolation' [patent_app_type] => new [patent_app_number] => 10/096867 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036246.pdf [firstpage_image] =>[orig_patent_app_number] => 10096867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096867
Manufacturing method of semiconductor device having trench type element isolation Mar 13, 2002 Issued
Array ( [id] => 1245659 [patent_doc_number] => 06677187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Process for encapsulating an electrical or electronic component in a sealed manner' [patent_app_type] => B2 [patent_app_number] => 10/068576 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3627 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677187.pdf [firstpage_image] =>[orig_patent_app_number] => 10068576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068576
Process for encapsulating an electrical or electronic component in a sealed manner Feb 4, 2002 Issued
Array ( [id] => 1163272 [patent_doc_number] => 06759310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method for making a semiconductor substrate comprising a variant porous layer' [patent_app_type] => B2 [patent_app_number] => 10/067486 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 8660 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759310.pdf [firstpage_image] =>[orig_patent_app_number] => 10067486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067486
Method for making a semiconductor substrate comprising a variant porous layer Feb 3, 2002 Issued
Array ( [id] => 602363 [patent_doc_number] => 07432126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Substrate with semiconductor layer, electronic component, electronic circuit, printable composition and method for production thereof' [patent_app_type] => utility [patent_app_number] => 10/432767 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432126.pdf [firstpage_image] =>[orig_patent_app_number] => 10432767 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/432767
Substrate with semiconductor layer, electronic component, electronic circuit, printable composition and method for production thereof Nov 29, 2001 Issued
Array ( [id] => 1381897 [patent_doc_number] => 06551893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Atomic layer deposition of capacitor dielectric' [patent_app_type] => B1 [patent_app_number] => 09/994547 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2286 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551893.pdf [firstpage_image] =>[orig_patent_app_number] => 09994547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994547
Atomic layer deposition of capacitor dielectric Nov 26, 2001 Issued
Array ( [id] => 1210875 [patent_doc_number] => 06713817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Semiconductor integrated circuit system' [patent_app_type] => B2 [patent_app_number] => 10/004077 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 7275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713817.pdf [firstpage_image] =>[orig_patent_app_number] => 10004077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004077
Semiconductor integrated circuit system Oct 29, 2001 Issued
Array ( [id] => 6237586 [patent_doc_number] => 20020043718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Sockets for module extension and memory system using same' [patent_app_type] => new [patent_app_number] => 09/978497 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3474 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043718.pdf [firstpage_image] =>[orig_patent_app_number] => 09978497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978497
Sockets for module extension and memory system using same Oct 15, 2001 Issued
Array ( [id] => 1177614 [patent_doc_number] => 06743733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Process for producing a semiconductor device including etching using a multi-step etching treatment having different gas compositions in each step' [patent_app_type] => B2 [patent_app_number] => 09/946507 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743733.pdf [firstpage_image] =>[orig_patent_app_number] => 09946507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946507
Process for producing a semiconductor device including etching using a multi-step etching treatment having different gas compositions in each step Sep 5, 2001 Issued
Array ( [id] => 1529375 [patent_doc_number] => 06479845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Pattern for routing power and ground for an integrated circuit chip' [patent_app_type] => B2 [patent_app_number] => 09/946984 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2537 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479845.pdf [firstpage_image] =>[orig_patent_app_number] => 09946984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946984
Pattern for routing power and ground for an integrated circuit chip Sep 5, 2001 Issued
Array ( [id] => 1192988 [patent_doc_number] => 06730575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure' [patent_app_type] => B2 [patent_app_number] => 09/945137 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 5211 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730575.pdf [firstpage_image] =>[orig_patent_app_number] => 09945137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945137
Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure Aug 29, 2001 Issued
Array ( [id] => 6778801 [patent_doc_number] => 20030049882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Wire bonded microelectronic device assemblies and methods of manufacturing same' [patent_app_type] => new [patent_app_number] => 09/943897 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4627 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049882.pdf [firstpage_image] =>[orig_patent_app_number] => 09943897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943897
Method of manufacturing wire bonded microelectronic device assemblies Aug 29, 2001 Issued
Array ( [id] => 1133943 [patent_doc_number] => 06784018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry' [patent_app_type] => B2 [patent_app_number] => 09/943187 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2797 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784018.pdf [firstpage_image] =>[orig_patent_app_number] => 09943187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943187
Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry Aug 28, 2001 Issued
Array ( [id] => 6692698 [patent_doc_number] => 20030040130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method for selection of parameters for implant anneal of patterned semiconductor substrates and specification of a laser system' [patent_app_type] => new [patent_app_number] => 09/927247 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12758 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040130.pdf [firstpage_image] =>[orig_patent_app_number] => 09927247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927247
Method for selection of parameters for implant anneal of patterned semiconductor substrates and specification of a laser system Aug 8, 2001 Abandoned
Array ( [id] => 1424386 [patent_doc_number] => 06503815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/920757 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503815.pdf [firstpage_image] =>[orig_patent_app_number] => 09920757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920757
Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation Aug 2, 2001 Issued
Array ( [id] => 1340166 [patent_doc_number] => 06589875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same' [patent_app_type] => B1 [patent_app_number] => 09/920997 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4142 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589875.pdf [firstpage_image] =>[orig_patent_app_number] => 09920997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920997
Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same Aug 1, 2001 Issued
Array ( [id] => 1600405 [patent_doc_number] => 06475881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Fabrication process of a semiconductor device including a dicing process of a semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/916445 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4816 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475881.pdf [firstpage_image] =>[orig_patent_app_number] => 09916445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916445
Fabrication process of a semiconductor device including a dicing process of a semiconductor wafer Jul 29, 2001 Issued
Array ( [id] => 5798523 [patent_doc_number] => 20020008269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Structure of a stacked memory cell, in particular a ferroelectric cell' [patent_app_type] => new [patent_app_number] => 09/911637 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2672 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008269.pdf [firstpage_image] =>[orig_patent_app_number] => 09911637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911637
Method of fabricating a ferroelectric stacked memory cell Jul 22, 2001 Issued
Menu