
Khanh B. Duong
Examiner (ID: 11457)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 696 |
| Issued Applications | 594 |
| Pending Applications | 7 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6392137
[patent_doc_number] => 20100163847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS'
[patent_app_type] => utility
[patent_app_number] => 12/347268
[patent_app_country] => US
[patent_app_date] => 2008-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10811
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20100163847.pdf
[firstpage_image] =>[orig_patent_app_number] => 12347268
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/347268 | Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains | Dec 30, 2008 | Issued |
Array
(
[id] => 6280482
[patent_doc_number] => 20100155893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'Method for Forming Thin Film Resistor and Terminal Bond Pad Simultaneously'
[patent_app_type] => utility
[patent_app_number] => 12/342430
[patent_app_country] => US
[patent_app_date] => 2008-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4584
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20100155893.pdf
[firstpage_image] =>[orig_patent_app_number] => 12342430
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/342430 | Method for forming thin film resistor and terminal bond pad simultaneously | Dec 22, 2008 | Issued |
Array
(
[id] => 5502280
[patent_doc_number] => 20090162968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'Method and apparatus for producing a semitransparent photovoltaic module'
[patent_app_type] => utility
[patent_app_number] => 12/317377
[patent_app_country] => US
[patent_app_date] => 2008-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3693
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20090162968.pdf
[firstpage_image] =>[orig_patent_app_number] => 12317377
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/317377 | Method and apparatus for producing a semitransparent photovoltaic module | Dec 21, 2008 | Abandoned |
Array
(
[id] => 8294335
[patent_doc_number] => 08222118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-17
[patent_title] => 'Wafer backside grinding with stress relief'
[patent_app_type] => utility
[patent_app_number] => 12/335378
[patent_app_country] => US
[patent_app_date] => 2008-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 2676
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12335378
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/335378 | Wafer backside grinding with stress relief | Dec 14, 2008 | Issued |
Array
(
[id] => 7801000
[patent_doc_number] => 08129270
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-03-06
[patent_title] => 'Method for depositing tungsten film having low resistivity, low roughness and high reflectivity'
[patent_app_type] => utility
[patent_app_number] => 12/332017
[patent_app_country] => US
[patent_app_date] => 2008-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5060
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/129/08129270.pdf
[firstpage_image] =>[orig_patent_app_number] => 12332017
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/332017 | Method for depositing tungsten film having low resistivity, low roughness and high reflectivity | Dec 9, 2008 | Issued |
Array
(
[id] => 210437
[patent_doc_number] => 07625798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Method of producing semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 12/314107
[patent_app_country] => US
[patent_app_date] => 2008-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 5137
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/625/07625798.pdf
[firstpage_image] =>[orig_patent_app_number] => 12314107
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/314107 | Method of producing semiconductor memory | Dec 3, 2008 | Issued |
Array
(
[id] => 5282342
[patent_doc_number] => 20090096016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Method of manufacturing a sonos device'
[patent_app_type] => utility
[patent_app_number] => 12/314017
[patent_app_country] => US
[patent_app_date] => 2008-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2104
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20090096016.pdf
[firstpage_image] =>[orig_patent_app_number] => 12314017
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/314017 | Method of manufacturing a sonos device | Dec 1, 2008 | Abandoned |
Array
(
[id] => 5319825
[patent_doc_number] => 20090057815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'FORMING CHANNEL STOP FOR DEEP TRENCH ISOLATION PRIOR TO DEEP TRENCH ETCH'
[patent_app_type] => utility
[patent_app_number] => 12/263646
[patent_app_country] => US
[patent_app_date] => 2008-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2131
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20090057815.pdf
[firstpage_image] =>[orig_patent_app_number] => 12263646
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/263646 | FORMING CHANNEL STOP FOR DEEP TRENCH ISOLATION PRIOR TO DEEP TRENCH ETCH | Nov 2, 2008 | Abandoned |
Array
(
[id] => 1076882
[patent_doc_number] => 07615393
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-11-10
[patent_title] => 'Methods of forming multi-doped junctions on a substrate'
[patent_app_type] => utility
[patent_app_number] => 12/260507
[patent_app_country] => US
[patent_app_date] => 2008-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 27
[patent_no_of_words] => 7211
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/615/07615393.pdf
[firstpage_image] =>[orig_patent_app_number] => 12260507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/260507 | Methods of forming multi-doped junctions on a substrate | Oct 28, 2008 | Issued |
Array
(
[id] => 6448685
[patent_doc_number] => 20100105185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'REDUCING POLY-DEPLETION THROUGH CO-IMPLANTING CARBON AND NITROGEN'
[patent_app_type] => utility
[patent_app_number] => 12/259028
[patent_app_country] => US
[patent_app_date] => 2008-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3266
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20100105185.pdf
[firstpage_image] =>[orig_patent_app_number] => 12259028
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/259028 | Reducing poly-depletion through co-implanting carbon and nitrogen | Oct 26, 2008 | Issued |
Array
(
[id] => 4569216
[patent_doc_number] => 07858515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Method for forming metal line in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/247517
[patent_app_country] => US
[patent_app_date] => 2008-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2045
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/858/07858515.pdf
[firstpage_image] =>[orig_patent_app_number] => 12247517
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/247517 | Method for forming metal line in semiconductor device | Oct 7, 2008 | Issued |
Array
(
[id] => 8629768
[patent_doc_number] => 08361840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-29
[patent_title] => 'Thermal barrier layer for integrated circuit manufacture'
[patent_app_type] => utility
[patent_app_number] => 12/236907
[patent_app_country] => US
[patent_app_date] => 2008-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 8113
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12236907
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/236907 | Thermal barrier layer for integrated circuit manufacture | Sep 23, 2008 | Issued |
Array
(
[id] => 5416446
[patent_doc_number] => 20090042333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'Structure and Method for Surfaced-Passivated Zinc-Oxide'
[patent_app_type] => utility
[patent_app_number] => 12/199378
[patent_app_country] => US
[patent_app_date] => 2008-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2603
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20090042333.pdf
[firstpage_image] =>[orig_patent_app_number] => 12199378
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/199378 | Method for surfaced-passivated zinc-oxide | Aug 26, 2008 | Issued |
Array
(
[id] => 7724235
[patent_doc_number] => 08097505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-17
[patent_title] => 'Method of forming isolation layer in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/197267
[patent_app_country] => US
[patent_app_date] => 2008-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 3510
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/097/08097505.pdf
[firstpage_image] =>[orig_patent_app_number] => 12197267
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/197267 | Method of forming isolation layer in semiconductor device | Aug 23, 2008 | Issued |
Array
(
[id] => 4483815
[patent_doc_number] => 07902056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Plasma treated metal silicide layer formation'
[patent_app_type] => utility
[patent_app_number] => 12/195307
[patent_app_country] => US
[patent_app_date] => 2008-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 3341
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/902/07902056.pdf
[firstpage_image] =>[orig_patent_app_number] => 12195307
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195307 | Plasma treated metal silicide layer formation | Aug 19, 2008 | Issued |
Array
(
[id] => 5319687
[patent_doc_number] => 20090057677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'FERROELECTRIC DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/193238
[patent_app_country] => US
[patent_app_date] => 2008-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4861
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20090057677.pdf
[firstpage_image] =>[orig_patent_app_number] => 12193238
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/193238 | FERROELECTRIC DEVICE AND METHOD FOR FABRICATING THE SAME | Aug 17, 2008 | Abandoned |
Array
(
[id] => 152324
[patent_doc_number] => 07683434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Preventing cavitation in high aspect ratio dielectric regions of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/190777
[patent_app_country] => US
[patent_app_date] => 2008-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 1791
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/683/07683434.pdf
[firstpage_image] =>[orig_patent_app_number] => 12190777
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/190777 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | Aug 12, 2008 | Issued |
Array
(
[id] => 6473886
[patent_doc_number] => 20100041230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-18
[patent_title] => 'METHODS FOR FORMING COPPER INTERCONNECTS FOR SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/190428
[patent_app_country] => US
[patent_app_date] => 2008-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3413
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20100041230.pdf
[firstpage_image] =>[orig_patent_app_number] => 12190428
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/190428 | Methods for forming copper interconnects for semiconductor devices | Aug 11, 2008 | Issued |
Array
(
[id] => 6247136
[patent_doc_number] => 20100025727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'ENHANCED SPONTANEOUS SEPARATION METHOD FOR PRODUCTION OF FREE-STANDING NITRIDE THIN FILMS, SUBSTRATES, AND HETEROSTRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 12/185607
[patent_app_country] => US
[patent_app_date] => 2008-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7123
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20100025727.pdf
[firstpage_image] =>[orig_patent_app_number] => 12185607
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/185607 | ENHANCED SPONTANEOUS SEPARATION METHOD FOR PRODUCTION OF FREE-STANDING NITRIDE THIN FILMS, SUBSTRATES, AND HETEROSTRUCTURES | Aug 3, 2008 | Abandoned |
Array
(
[id] => 6247297
[patent_doc_number] => 20100025830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/185058
[patent_app_country] => US
[patent_app_date] => 2008-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20100025830.pdf
[firstpage_image] =>[orig_patent_app_number] => 12185058
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/185058 | Method for forming an etched recess package on package system | Jul 31, 2008 | Issued |