Search

Khareem E. Almo

Examiner (ID: 13774, Phone: (571)272-5524 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2849, 2836, 2816, 2842
Total Applications
1065
Issued Applications
903
Pending Applications
64
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8739049 [patent_doc_number] => 08410824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Buffer with active output impedance matching' [patent_app_type] => utility [patent_app_number] => 12/604186 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5831 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12604186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604186
Buffer with active output impedance matching Oct 21, 2009 Issued
Array ( [id] => 6036942 [patent_doc_number] => 20110089991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'RF BUFFER CIRCUIT WITH DYNAMIC BIASING' [patent_app_type] => utility [patent_app_number] => 12/603379 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5324 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089991.pdf [firstpage_image] =>[orig_patent_app_number] => 12603379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603379
RF buffer circuit with dynamic biasing Oct 20, 2009 Issued
Array ( [id] => 6121673 [patent_doc_number] => 20110084734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'CIRCUIT HAVING SAMPLE AND HOLD FEEDBACK CONTROL AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/579014 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7238 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084734.pdf [firstpage_image] =>[orig_patent_app_number] => 12579014 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579014
Circuit having sample and hold feedback control and method Oct 13, 2009 Issued
Array ( [id] => 6248211 [patent_doc_number] => 20100026351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops' [patent_app_type] => utility [patent_app_number] => 12/574847 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5090 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20100026351.pdf [firstpage_image] =>[orig_patent_app_number] => 12574847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574847
System and method to improve the efficiency of synchronous mirror delays and delay locked loops Oct 6, 2009 Issued
Array ( [id] => 6339296 [patent_doc_number] => 20100019822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'DELAY LINE SYNCHRONIZER APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/568525 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7973 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019822.pdf [firstpage_image] =>[orig_patent_app_number] => 12568525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568525
Delay line synchronizer apparatus and method Sep 27, 2009 Issued
Array ( [id] => 8116105 [patent_doc_number] => 08159273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Transmission circuit' [patent_app_type] => utility [patent_app_number] => 12/566217 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5876 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159273.pdf [firstpage_image] =>[orig_patent_app_number] => 12566217 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566217
Transmission circuit Sep 23, 2009 Issued
Array ( [id] => 5973174 [patent_doc_number] => 20110068837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER' [patent_app_type] => utility [patent_app_number] => 12/565624 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3853 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20110068837.pdf [firstpage_image] =>[orig_patent_app_number] => 12565624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565624
Apparatus and method to tolerate floating input pin for input buffer Sep 22, 2009 Issued
Array ( [id] => 6361630 [patent_doc_number] => 20100079176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Inverter Driver And Load Driver Including The Same, And Driving Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/564632 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7312 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079176.pdf [firstpage_image] =>[orig_patent_app_number] => 12564632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564632
Inverter driver and load driver including the same, and driving method thereof Sep 21, 2009 Issued
Array ( [id] => 6386111 [patent_doc_number] => 20100176848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'INPUT/OUTPUT BUFFER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/505274 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20100176848.pdf [firstpage_image] =>[orig_patent_app_number] => 12505274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/505274
Input/output buffer circuit Jul 16, 2009 Issued
Array ( [id] => 8190704 [patent_doc_number] => 08183892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Monolithic low impedance dual gate current sense MOSFET' [patent_app_type] => utility [patent_app_number] => 12/479613 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4875 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183892.pdf [firstpage_image] =>[orig_patent_app_number] => 12479613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479613
Monolithic low impedance dual gate current sense MOSFET Jun 4, 2009 Issued
Array ( [id] => 8206125 [patent_doc_number] => 08190102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Programmable antenna with configuration control and methods for use therewith' [patent_app_type] => utility [patent_app_number] => 12/468231 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 9803 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190102.pdf [firstpage_image] =>[orig_patent_app_number] => 12468231 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468231
Programmable antenna with configuration control and methods for use therewith May 18, 2009 Issued
Array ( [id] => 5552506 [patent_doc_number] => 20090286492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'RF SWITCH AND TRANSMIT AND RECEIVE MODULE COMPRISING SUCH A SWITCH' [patent_app_type] => utility [patent_app_number] => 12/467994 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3438 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20090286492.pdf [firstpage_image] =>[orig_patent_app_number] => 12467994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467994
RF SWITCH AND TRANSMIT AND RECEIVE MODULE COMPRISING SUCH A SWITCH May 17, 2009 Abandoned
Array ( [id] => 8437430 [patent_doc_number] => 08285209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Short range FM modulator/transmitter and system incorporating same' [patent_app_type] => utility [patent_app_number] => 12/514152 [patent_app_country] => US [patent_app_date] => 2009-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12514152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/514152
Short range FM modulator/transmitter and system incorporating same May 7, 2009 Issued
Array ( [id] => 8798916 [patent_doc_number] => 08437798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Uplink scheduling support in multi-carrier wireless communication systems' [patent_app_type] => utility [patent_app_number] => 12/430883 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5553 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12430883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430883
Uplink scheduling support in multi-carrier wireless communication systems Apr 26, 2009 Issued
Array ( [id] => 6539550 [patent_doc_number] => 20100271100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'MINIMAL BUBBLE VOLTAGE REGULATOR' [patent_app_type] => utility [patent_app_number] => 12/430829 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271100.pdf [firstpage_image] =>[orig_patent_app_number] => 12430829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430829
Minimal bubble voltage regulator Apr 26, 2009 Issued
Array ( [id] => 6414541 [patent_doc_number] => 20100141323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'DELAY LINE' [patent_app_type] => utility [patent_app_number] => 12/425710 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11106 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20100141323.pdf [firstpage_image] =>[orig_patent_app_number] => 12425710 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425710
DELAY LINE Apr 16, 2009 Abandoned
Array ( [id] => 6488357 [patent_doc_number] => 20100259303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'REFERENCE BUFFER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/420998 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259303.pdf [firstpage_image] =>[orig_patent_app_number] => 12420998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/420998
Reference buffer circuit Apr 8, 2009 Issued
Array ( [id] => 5313986 [patent_doc_number] => 20090278584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'CELL-BASED INTEGRATED CIRCUIT AND A METHOD OF OPERATING A THYRISTOR CIRCUIT IN A STANDARD CELL OF A CELL-BASED INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/416200 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4955 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20090278584.pdf [firstpage_image] =>[orig_patent_app_number] => 12416200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416200
Cell-based integrated circuit and a method of operating a thyristor circuit in a standard cell of a cell-based integrated circuit Mar 31, 2009 Issued
Array ( [id] => 6324437 [patent_doc_number] => 20100244907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'LOW SPEED, LOAD INDEPENDENT, SLEW RATE CONTROLLED OUTPUT BUFFER WITH NO DC POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 12/410848 [patent_app_country] => US [patent_app_date] => 2009-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1624 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244907.pdf [firstpage_image] =>[orig_patent_app_number] => 12410848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/410848
Low speed, load independent, slew rate controlled output buffer with no DC power consumption Mar 24, 2009 Issued
Array ( [id] => 6025212 [patent_doc_number] => 20110053538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => ' HIGH SPEED FREQUENCY DETECTOR' [patent_app_type] => utility [patent_app_number] => 12/513621 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20110053538.pdf [firstpage_image] =>[orig_patent_app_number] => 12513621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/513621
High speed frequency detector Mar 19, 2009 Issued
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