
Khareem E. Almo
Examiner (ID: 12419, Phone: (571)272-5524 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2842, 2849, 2816 |
| Total Applications | 1041 |
| Issued Applications | 887 |
| Pending Applications | 71 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7778453
[patent_doc_number] => 08121560
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-21
[patent_title] => 'Pre-distortion with enhanced convergence for linearization'
[patent_app_type] => utility
[patent_app_number] => 12/257313
[patent_app_country] => US
[patent_app_date] => 2008-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 8359
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/121/08121560.pdf
[firstpage_image] =>[orig_patent_app_number] => 12257313
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/257313 | Pre-distortion with enhanced convergence for linearization | Oct 22, 2008 | Issued |
Array
(
[id] => 6589243
[patent_doc_number] => 20100048150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'APPARATUS AND METHOD FOR FEEDFORWARD-TYPE PHASE NOISE ELIMINATION IN PORTABLE TERMINAL'
[patent_app_type] => utility
[patent_app_number] => 12/255136
[patent_app_country] => US
[patent_app_date] => 2008-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8903
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20100048150.pdf
[firstpage_image] =>[orig_patent_app_number] => 12255136
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/255136 | Apparatus and method for feedforward-type phase noise elimination in portable terminal | Oct 20, 2008 | Issued |
Array
(
[id] => 6610901
[patent_doc_number] => 20100099372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'TUNABLE FILTERS WITH LOWER RESIDUAL SIDEBAND'
[patent_app_type] => utility
[patent_app_number] => 12/254129
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9145
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20100099372.pdf
[firstpage_image] =>[orig_patent_app_number] => 12254129
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/254129 | Tunable filters with lower residual sideband | Oct 19, 2008 | Issued |
Array
(
[id] => 8400631
[patent_doc_number] => 08271025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-18
[patent_title] => 'Device network technology selection and display in multi-technology wireless environments'
[patent_app_type] => utility
[patent_app_number] => 12/254704
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 15583
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12254704
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/254704 | Device network technology selection and display in multi-technology wireless environments | Oct 19, 2008 | Issued |
Array
(
[id] => 8107859
[patent_doc_number] => 08155581
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'Method and system for exhibiting media segments'
[patent_app_type] => utility
[patent_app_number] => 12/253950
[patent_app_country] => US
[patent_app_date] => 2008-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4180
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/155/08155581.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253950
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253950 | Method and system for exhibiting media segments | Oct 17, 2008 | Issued |
Array
(
[id] => 5276071
[patent_doc_number] => 20090128203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'PLL-BASED TIMING-SIGNAL GENERATOR AND METHOD OF GENERATING TIMING SIGNAL BY SAME'
[patent_app_type] => utility
[patent_app_number] => 12/253551
[patent_app_country] => US
[patent_app_date] => 2008-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5603
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20090128203.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253551
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253551 | PLL-based timing-signal generator and method of generating timing signal by same | Oct 16, 2008 | Issued |
Array
(
[id] => 6610681
[patent_doc_number] => 20100099358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'SYNCHRONIZING WAKEUP OPERATIONS IN ELECTRONIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/253057
[patent_app_country] => US
[patent_app_date] => 2008-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8299
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20100099358.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253057
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253057 | Synchronizing wakeup operations in electronic devices | Oct 15, 2008 | Issued |
Array
(
[id] => 5543349
[patent_doc_number] => 20090153226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'HIGH-SIDE DRIVER FOR PROVIDING AN OFF-STATE IN CASE OF GROUND LOSS'
[patent_app_type] => utility
[patent_app_number] => 12/253002
[patent_app_country] => US
[patent_app_date] => 2008-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2298
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20090153226.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253002
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253002 | HIGH-SIDE DRIVER FOR PROVIDING AN OFF-STATE IN CASE OF GROUND LOSS | Oct 15, 2008 | Abandoned |
Array
(
[id] => 8872363
[patent_doc_number] => 08467749
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-18
[patent_title] => 'Monolithic FM-band transmit power amplifier for mobile cellular devices and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 12/253205
[patent_app_country] => US
[patent_app_date] => 2008-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3237
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12253205
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253205 | Monolithic FM-band transmit power amplifier for mobile cellular devices and method of operation thereof | Oct 15, 2008 | Issued |
Array
(
[id] => 4463298
[patent_doc_number] => 07880517
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Delayed-locked loop with power-saving function'
[patent_app_type] => utility
[patent_app_number] => 12/253211
[patent_app_country] => US
[patent_app_date] => 2008-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3007
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/880/07880517.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253211
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253211 | Delayed-locked loop with power-saving function | Oct 15, 2008 | Issued |
Array
(
[id] => 5502457
[patent_doc_number] => 20090163145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'SYSTEMS AND METHODS FOR TIME OPTIMIZATION FOR SILENCING WIRELESS DEVICES IN COEXISTENCE NETWORKS'
[patent_app_type] => utility
[patent_app_number] => 12/251187
[patent_app_country] => US
[patent_app_date] => 2008-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8192
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20090163145.pdf
[firstpage_image] =>[orig_patent_app_number] => 12251187
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/251187 | Systems and methods for time optimization for silencing wireless devices in coexistence networks | Oct 13, 2008 | Issued |
Array
(
[id] => 5283917
[patent_doc_number] => 20090097591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'APPARATUS AND METHOD FOR ENVELOPE TRACKING POWER AMPLIFICATION IN WIRELESS COMMUNICATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/249079
[patent_app_country] => US
[patent_app_date] => 2008-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3432
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20090097591.pdf
[firstpage_image] =>[orig_patent_app_number] => 12249079
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/249079 | APPARATUS AND METHOD FOR ENVELOPE TRACKING POWER AMPLIFICATION IN WIRELESS COMMUNICATION SYSTEM | Oct 9, 2008 | Abandoned |
Array
(
[id] => 103541
[patent_doc_number] => 07728655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-01
[patent_title] => 'Current limiting load switch with dynamically generated tracking reference voltage'
[patent_app_type] => utility
[patent_app_number] => 12/249162
[patent_app_country] => US
[patent_app_date] => 2008-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5734
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/728/07728655.pdf
[firstpage_image] =>[orig_patent_app_number] => 12249162
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/249162 | Current limiting load switch with dynamically generated tracking reference voltage | Oct 9, 2008 | Issued |
Array
(
[id] => 5478111
[patent_doc_number] => 20090201068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'Output circuit with overshoot-reducing function'
[patent_app_type] => utility
[patent_app_number] => 12/246479
[patent_app_country] => US
[patent_app_date] => 2008-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4864
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20090201068.pdf
[firstpage_image] =>[orig_patent_app_number] => 12246479
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/246479 | Output circuit with overshoot-reducing function | Oct 5, 2008 | Issued |
Array
(
[id] => 4645135
[patent_doc_number] => 08022744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-20
[patent_title] => 'Signal generator'
[patent_app_type] => utility
[patent_app_number] => 12/244900
[patent_app_country] => US
[patent_app_date] => 2008-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5588
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/022/08022744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12244900
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/244900 | Signal generator | Oct 2, 2008 | Issued |
Array
(
[id] => 5358577
[patent_doc_number] => 20090033371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'AMPLIFIER CIRCUIT FOR DOUBLE SAMPLED ARCHITECTURES'
[patent_app_type] => utility
[patent_app_number] => 12/244214
[patent_app_country] => US
[patent_app_date] => 2008-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20090033371.pdf
[firstpage_image] =>[orig_patent_app_number] => 12244214
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/244214 | Amplifier circuit for double sampled architectures | Oct 1, 2008 | Issued |
Array
(
[id] => 83248
[patent_doc_number] => 07746136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-29
[patent_title] => 'Frequency-doubling delay locked loop'
[patent_app_type] => utility
[patent_app_number] => 12/284763
[patent_app_country] => US
[patent_app_date] => 2008-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5240
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/746/07746136.pdf
[firstpage_image] =>[orig_patent_app_number] => 12284763
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/284763 | Frequency-doubling delay locked loop | Sep 24, 2008 | Issued |
Array
(
[id] => 5426334
[patent_doc_number] => 20090085644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 12/234398
[patent_app_country] => US
[patent_app_date] => 2008-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5539
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20090085644.pdf
[firstpage_image] =>[orig_patent_app_number] => 12234398
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/234398 | Integrated circuit | Sep 18, 2008 | Issued |
Array
(
[id] => 55441
[patent_doc_number] => 07768329
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/211187
[patent_app_country] => US
[patent_app_date] => 2008-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 31
[patent_no_of_words] => 9851
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/768/07768329.pdf
[firstpage_image] =>[orig_patent_app_number] => 12211187
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/211187 | Semiconductor device | Sep 15, 2008 | Issued |
Array
(
[id] => 4850188
[patent_doc_number] => 20080315930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/203700
[patent_app_country] => US
[patent_app_date] => 2008-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10805
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0315/20080315930.pdf
[firstpage_image] =>[orig_patent_app_number] => 12203700
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/203700 | Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit | Sep 2, 2008 | Issued |