Search

Khareem E. Almo

Examiner (ID: 13774, Phone: (571)272-5524 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2849, 2836, 2816, 2842
Total Applications
1065
Issued Applications
903
Pending Applications
64
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4850188 [patent_doc_number] => 20080315930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/203700 [patent_app_country] => US [patent_app_date] => 2008-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10805 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315930.pdf [firstpage_image] =>[orig_patent_app_number] => 12203700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203700
Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit Sep 2, 2008 Issued
Array ( [id] => 6248209 [patent_doc_number] => 20100026349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SQUARE TO PSEUDO-SINUSOIDAL CLOCK CONVERSION CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/183550 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20100026349.pdf [firstpage_image] =>[orig_patent_app_number] => 12183550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183550
Square to pseudo-sinusoidal clock conversion circuit and method Jul 30, 2008 Issued
Array ( [id] => 4466296 [patent_doc_number] => 07936208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Bias circuit for a MOS device' [patent_app_type] => utility [patent_app_number] => 12/184148 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1773 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936208.pdf [firstpage_image] =>[orig_patent_app_number] => 12184148 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184148
Bias circuit for a MOS device Jul 30, 2008 Issued
Array ( [id] => 6248257 [patent_doc_number] => 20100026375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'CIRCUIT TO GENERATE CMOS LEVEL SIGNAL TO TRACK CORE SUPPLY VOLTAGE (VDD) LEVEL' [patent_app_type] => utility [patent_app_number] => 12/181334 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20100026375.pdf [firstpage_image] =>[orig_patent_app_number] => 12181334 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181334
CIRCUIT TO GENERATE CMOS LEVEL SIGNAL TO TRACK CORE SUPPLY VOLTAGE (VDD) LEVEL Jul 28, 2008 Abandoned
Array ( [id] => 6339230 [patent_doc_number] => 20100019806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'STACKED CASCODE CURRENT SOURCE' [patent_app_type] => utility [patent_app_number] => 12/180947 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019806.pdf [firstpage_image] =>[orig_patent_app_number] => 12180947 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180947
Stacked cascode current source Jul 27, 2008 Issued
Array ( [id] => 5302226 [patent_doc_number] => 20090296878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'FREQUENCY DIVIDER' [patent_app_type] => utility [patent_app_number] => 12/179581 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296878.pdf [firstpage_image] =>[orig_patent_app_number] => 12179581 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179581
Frequency divider Jul 24, 2008 Issued
Array ( [id] => 6339196 [patent_doc_number] => 20100019800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'VERNIER PHASE ERROR DETECTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/178677 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2611 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019800.pdf [firstpage_image] =>[orig_patent_app_number] => 12178677 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/178677
VERNIER PHASE ERROR DETECTION METHOD Jul 23, 2008 Abandoned
Array ( [id] => 5358580 [patent_doc_number] => 20090033374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Clock generator' [patent_app_type] => utility [patent_app_number] => 12/219129 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2996 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20090033374.pdf [firstpage_image] =>[orig_patent_app_number] => 12219129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219129
Clock generator Jul 15, 2008 Abandoned
Array ( [id] => 7776175 [patent_doc_number] => 08120416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/166085 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6601 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120416.pdf [firstpage_image] =>[orig_patent_app_number] => 12166085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166085
Semiconductor integrated circuit Jun 30, 2008 Issued
Array ( [id] => 6371483 [patent_doc_number] => 20100315182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'ISOLATING INTERFACE WITH A DIFFERENTIATING CIRCUIT COMPRISING A CAPACITIVE BARRIER AND METHOD FOR TRANSMITTING A SIGNAL BY MEANS OF SUCH ISOLATING INTERFACE' [patent_app_type] => utility [patent_app_number] => 12/452229 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5042 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315182.pdf [firstpage_image] =>[orig_patent_app_number] => 12452229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/452229
Isolating interface with a differentiating circuit comprising a capacitive barrier and method for transmitting a signal by means of such isolating interface Jun 19, 2008 Issued
Array ( [id] => 143520 [patent_doc_number] => 07692474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Control circuit for a high-side semiconductor switch for switching a supply voltage' [patent_app_type] => utility [patent_app_number] => 12/126405 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692474.pdf [firstpage_image] =>[orig_patent_app_number] => 12126405 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126405
Control circuit for a high-side semiconductor switch for switching a supply voltage May 22, 2008 Issued
Array ( [id] => 5512541 [patent_doc_number] => 20090212845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'High Voltage Control Switch' [patent_app_type] => utility [patent_app_number] => 12/119305 [patent_app_country] => US [patent_app_date] => 2008-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212845.pdf [firstpage_image] =>[orig_patent_app_number] => 12119305 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119305
High Voltage Control Switch May 11, 2008 Abandoned
Array ( [id] => 4673927 [patent_doc_number] => 20080211555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Delay locked loop in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/150904 [patent_app_country] => US [patent_app_date] => 2008-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6776 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211555.pdf [firstpage_image] =>[orig_patent_app_number] => 12150904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/150904
Delay locked loop in semiconductor memory device Apr 30, 2008 Issued
Array ( [id] => 4958391 [patent_doc_number] => 20080272815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'DUTY CYCLE CORRECTION CIRCUITS INCLUDING A TRANSITION GENERATOR CIRCUIT FOR GENERATING TRANSITIONS IN A DUTY CYCLE CORRECTED SIGNAL RESPONSIVE TO AN INPUT SIGNAL AND A DELAYED VERSION OF THE INPUT SIGNAL AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/112225 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5724 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272815.pdf [firstpage_image] =>[orig_patent_app_number] => 12112225 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112225
Duty cycle correction circuits including a transition generator circuit for generating transitions in a duty cycle corrected signal responsive to an input signal and a delayed version of the input signal and methods of operating the same Apr 29, 2008 Issued
Array ( [id] => 8630732 [patent_doc_number] => 08362810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Local interconnect network receiver' [patent_app_type] => utility [patent_app_number] => 12/597239 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12597239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/597239
Local interconnect network receiver Apr 22, 2008 Issued
Array ( [id] => 5567828 [patent_doc_number] => 20090251206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/061812 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3304 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20090251206.pdf [firstpage_image] =>[orig_patent_app_number] => 12061812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061812
Integrated circuit and method for manufacturing the same Apr 2, 2008 Issued
Array ( [id] => 4463364 [patent_doc_number] => 07880533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Bandgap voltage reference circuit' [patent_app_type] => utility [patent_app_number] => 12/054875 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4377 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880533.pdf [firstpage_image] =>[orig_patent_app_number] => 12054875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054875
Bandgap voltage reference circuit Mar 24, 2008 Issued
Array ( [id] => 5470547 [patent_doc_number] => 20090243713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'REFERENCE VOLTAGE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/054856 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4846 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243713.pdf [firstpage_image] =>[orig_patent_app_number] => 12054856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054856
Reference voltage circuit Mar 24, 2008 Issued
Array ( [id] => 191524 [patent_doc_number] => 07642838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Voltage redoubling circuit' [patent_app_type] => utility [patent_app_number] => 12/054233 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1935 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642838.pdf [firstpage_image] =>[orig_patent_app_number] => 12054233 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054233
Voltage redoubling circuit Mar 23, 2008 Issued
Array ( [id] => 5401837 [patent_doc_number] => 20090237150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'BANDGAP REFERENCE CIRCUIT WITH LOW OPERATING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/051989 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4711 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237150.pdf [firstpage_image] =>[orig_patent_app_number] => 12051989 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051989
Bandgap reference circuit with low operating voltage Mar 19, 2008 Issued
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