Search

Khareem E. Almo

Examiner (ID: 13774, Phone: (571)272-5524 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2849, 2836, 2816, 2842
Total Applications
1065
Issued Applications
903
Pending Applications
64
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8283602 [patent_doc_number] => 08217709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/510639 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4078 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11510639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510639
Semiconductor device Aug 27, 2006 Issued
Array ( [id] => 9524993 [patent_doc_number] => 08749271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Methods for synchronizing high-speed signals in a digital phase detector' [patent_app_type] => utility [patent_app_number] => 11/498365 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3932 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11498365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498365
Methods for synchronizing high-speed signals in a digital phase detector Aug 2, 2006 Issued
Array ( [id] => 583914 [patent_doc_number] => 07456666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Frequency-doubling delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/495212 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5206 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456666.pdf [firstpage_image] =>[orig_patent_app_number] => 11495212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495212
Frequency-doubling delay locked loop Jul 27, 2006 Issued
Array ( [id] => 4578536 [patent_doc_number] => 07830194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Centralizing the lock point of a synchronous circuit' [patent_app_type] => utility [patent_app_number] => 11/484163 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9895 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830194.pdf [firstpage_image] =>[orig_patent_app_number] => 11484163 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484163
Centralizing the lock point of a synchronous circuit Jul 10, 2006 Issued
Array ( [id] => 5623367 [patent_doc_number] => 20060261872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Accelerator Output Stage That Adjusts Drive Duration to Loading' [patent_app_type] => utility [patent_app_number] => 11/382995 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1038 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261872.pdf [firstpage_image] =>[orig_patent_app_number] => 11382995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382995
Accelerator output stage that adjusts drive duration to loading May 11, 2006 Issued
Array ( [id] => 5686336 [patent_doc_number] => 20060284651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Circuit and method of blocking access to a protected device' [patent_app_type] => utility [patent_app_number] => 11/430967 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284651.pdf [firstpage_image] =>[orig_patent_app_number] => 11430967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430967
Circuit and method of blocking access to a protected device May 9, 2006 Abandoned
Array ( [id] => 5450368 [patent_doc_number] => 20090066404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'MOSFET WITH TEMPERATURE SENSE FACILITY' [patent_app_type] => utility [patent_app_number] => 11/908664 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3192 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20090066404.pdf [firstpage_image] =>[orig_patent_app_number] => 11908664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/908664
MOSFET with temperature sense facility Mar 13, 2006 Issued
Array ( [id] => 5665122 [patent_doc_number] => 20060170472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Variable delay circuit' [patent_app_type] => utility [patent_app_number] => 11/367566 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11651 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170472.pdf [firstpage_image] =>[orig_patent_app_number] => 11367566 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367566
Variable delay circuit Mar 2, 2006 Abandoned
Array ( [id] => 5703548 [patent_doc_number] => 20060192595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/360996 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4878 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20060192595.pdf [firstpage_image] =>[orig_patent_app_number] => 11360996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360996
Sense amplifier Feb 23, 2006 Abandoned
Array ( [id] => 5020097 [patent_doc_number] => 20070146063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Differential amplifier circuit operable with wide range of input voltages' [patent_app_type] => utility [patent_app_number] => 11/360602 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6158 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146063.pdf [firstpage_image] =>[orig_patent_app_number] => 11360602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360602
Differential amplifier circuit operable with wide range of input voltages Feb 23, 2006 Abandoned
Array ( [id] => 8147364 [patent_doc_number] => 08164377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Signal dependent compensation with matched detectors' [patent_app_type] => utility [patent_app_number] => 11/354592 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 7599 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/164/08164377.pdf [firstpage_image] =>[orig_patent_app_number] => 11354592 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354592
Signal dependent compensation with matched detectors Feb 13, 2006 Issued
Array ( [id] => 5521675 [patent_doc_number] => 20090029656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'LIN BUS NETWORK, INTEGRATED CIRCUIT AND METHOD OF COMMUNICATING THEREON' [patent_app_type] => utility [patent_app_number] => 12/278484 [patent_app_country] => US [patent_app_date] => 2006-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4562 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029656.pdf [firstpage_image] =>[orig_patent_app_number] => 12278484 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/278484
LIN bus network, integrated circuit and method of communicating thereon Feb 8, 2006 Issued
Array ( [id] => 5175601 [patent_doc_number] => 20070176659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit' [patent_app_type] => utility [patent_app_number] => 11/341062 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10776 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176659.pdf [firstpage_image] =>[orig_patent_app_number] => 11341062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341062
Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit Jan 26, 2006 Issued
Array ( [id] => 5175597 [patent_doc_number] => 20070176655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Differential charge pump with open loop common mode' [patent_app_type] => utility [patent_app_number] => 11/342106 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176655.pdf [firstpage_image] =>[orig_patent_app_number] => 11342106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342106
Differential charge pump with open loop common mode Jan 26, 2006 Issued
Array ( [id] => 5869874 [patent_doc_number] => 20060164158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Reference voltage circuit' [patent_app_type] => utility [patent_app_number] => 11/337678 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 36055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164158.pdf [firstpage_image] =>[orig_patent_app_number] => 11337678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337678
Reference voltage circuit Jan 23, 2006 Issued
Array ( [id] => 5192240 [patent_doc_number] => 20070080722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Buffer' [patent_app_type] => utility [patent_app_number] => 11/275459 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080722.pdf [firstpage_image] =>[orig_patent_app_number] => 11275459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/275459
Buffer Jan 5, 2006 Abandoned
Array ( [id] => 353167 [patent_doc_number] => 07492193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Driver circuit' [patent_app_type] => utility [patent_app_number] => 11/325302 [patent_app_country] => US [patent_app_date] => 2006-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4384 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492193.pdf [firstpage_image] =>[orig_patent_app_number] => 11325302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325302
Driver circuit Jan 4, 2006 Issued
Array ( [id] => 5646483 [patent_doc_number] => 20060132215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Signal converting circuit' [patent_app_type] => utility [patent_app_number] => 11/312726 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2805 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20060132215.pdf [firstpage_image] =>[orig_patent_app_number] => 11312726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312726
Signal converting circuit Dec 18, 2005 Issued
Array ( [id] => 5077364 [patent_doc_number] => 20070120588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Low-jitter clock distribution' [patent_app_type] => utility [patent_app_number] => 11/291204 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3525 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120588.pdf [firstpage_image] =>[orig_patent_app_number] => 11291204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291204
Low-jitter clock distribution Nov 29, 2005 Abandoned
Array ( [id] => 5077359 [patent_doc_number] => 20070120583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'METHOD AND APPARATUS FOR FAST LOCKING OF A CLOCK GENERATING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/164622 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9301 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120583.pdf [firstpage_image] =>[orig_patent_app_number] => 11164622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164622
Method and apparatus for fast locking of a clock generating circuit Nov 29, 2005 Issued
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