Khareem E. Almo

Array ( [id] => 225445 [patent_doc_number] => 07605631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Delay line synchronizer apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/274857 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8031 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605631.pdf [firstpage_image] =>[orig_patent_app_number] => 11274857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 886471 [patent_doc_number] => 07352225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'DC offset reduction circuit and method' [patent_app_type] => utility [patent_app_number] => 11/164180 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2391 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352225.pdf [firstpage_image] =>[orig_patent_app_number] => 11164180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5664693 [patent_doc_number] => 20060170043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Resonant gate drive circuits' [patent_app_type] => utility [patent_app_number] => 11/266486 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 12787 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170043.pdf [firstpage_image] =>[orig_patent_app_number] => 11266486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 75710 [patent_doc_number] => 07750710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Delay circuit' [patent_app_type] => utility [patent_app_number] => 11/265104 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7906 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/750/07750710.pdf [firstpage_image] =>[orig_patent_app_number] => 11265104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5708511 [patent_doc_number] => 20060049855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/265087 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5252 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049855.pdf [firstpage_image] =>[orig_patent_app_number] => 11265087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5032238 [patent_doc_number] => 20070096777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Differential driver' [patent_app_type] => utility [patent_app_number] => 11/265690 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3307 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096777.pdf [firstpage_image] =>[orig_patent_app_number] => 11265690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5741537 [patent_doc_number] => 20060087260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Integrated circuit configuration for triggering power semiconductor switches' [patent_app_type] => utility [patent_app_number] => 11/247319 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2210 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087260.pdf [firstpage_image] =>[orig_patent_app_number] => 11247319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5192249 [patent_doc_number] => 20070080731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Duty cycle corrector' [patent_app_type] => utility [patent_app_number] => 11/247538 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2883 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080731.pdf [firstpage_image] =>[orig_patent_app_number] => 11247538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5806322 [patent_doc_number] => 20060092675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Power supply noise reduction circuit and power supply noise reduction method' [patent_app_type] => utility [patent_app_number] => 11/237909 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5342 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20060092675.pdf [firstpage_image] =>[orig_patent_app_number] => 11237909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5139521 [patent_doc_number] => 20070001737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'System and method of generating a clock cycle having an asymmetric duty cycle' [patent_app_type] => utility [patent_app_number] => 11/238779 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3135 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001737.pdf [firstpage_image] =>[orig_patent_app_number] => 11238779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5169362 [patent_doc_number] => 20070069793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method and system for high frequency clock signal gating' [patent_app_type] => utility [patent_app_number] => 11/235758 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1814 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069793.pdf [firstpage_image] =>[orig_patent_app_number] => 11235758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5169369 [patent_doc_number] => 20070069800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Negative charge-pump with circuit to eliminate parasitic diode turn-on' [patent_app_type] => utility [patent_app_number] => 11/233901 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4945 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069800.pdf [firstpage_image] =>[orig_patent_app_number] => 11233901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5578 [patent_doc_number] => 07816975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Circuit and method for bias voltage generation' [patent_app_type] => utility [patent_app_number] => 11/230786 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5468 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816975.pdf [firstpage_image] =>[orig_patent_app_number] => 11230786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5708502 [patent_doc_number] => 20060049846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Input/output circuit operated by variable operating voltage' [patent_app_type] => utility [patent_app_number] => 11/221536 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3649 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049846.pdf [firstpage_image] =>[orig_patent_app_number] => 11221536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8676327 [patent_doc_number] => 08384444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'I/O driver with pass gate feedback controlled output driver' [patent_app_type] => utility [patent_app_number] => 11/218937 [patent_app_country] => US [patent_app_date] => 2005-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1859 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11218937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 602981 [patent_doc_number] => 07432745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Gate driver circuit' [patent_app_type] => utility [patent_app_number] => 11/218384 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7393 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432745.pdf [firstpage_image] =>[orig_patent_app_number] => 11218384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 918696 [patent_doc_number] => 07323914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Charge pump circuit' [patent_app_type] => utility [patent_app_number] => 11/216605 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3460 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323914.pdf [firstpage_image] =>[orig_patent_app_number] => 11216605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4997954 [patent_doc_number] => 20070040588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Amplifier circuit for double sampled architectures' [patent_app_type] => utility [patent_app_number] => 11/206521 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040588.pdf [firstpage_image] =>[orig_patent_app_number] => 11206521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5152452 [patent_doc_number] => 20070035334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Comparator' [patent_app_type] => utility [patent_app_number] => 11/203096 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5024 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20070035334.pdf [firstpage_image] =>[orig_patent_app_number] => 11203096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 34016 [patent_doc_number] => 07791387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-07 [patent_title] => 'Fine-resolution edge-extending pulse width modulator' [patent_app_type] => utility [patent_app_number] => 11/204285 [patent_app_country] => US [patent_app_date] => 2005-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791387.pdf [firstpage_image] =>[orig_patent_app_number] => 11204285 [rel_patent_id] =>[rel_patent_doc_number] =>)