Search

Khareem E. Almo

Examiner (ID: 13774, Phone: (571)272-5524 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2849, 2836, 2816, 2842
Total Applications
1065
Issued Applications
903
Pending Applications
64
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5869830 [patent_doc_number] => 20060164143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method and system for reducing glitch effects within combinational logic' [patent_app_type] => utility [patent_app_number] => 11/041766 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4823 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164143.pdf [firstpage_image] =>[orig_patent_app_number] => 11041766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041766
Method and system for reducing glitch effects within combinational logic Jan 23, 2005 Issued
Array ( [id] => 7048895 [patent_doc_number] => 20050184782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Differential input receiver' [patent_app_type] => utility [patent_app_number] => 11/018275 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3590 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184782.pdf [firstpage_image] =>[orig_patent_app_number] => 11018275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018275
Differential input receiver Dec 20, 2004 Issued
Array ( [id] => 304126 [patent_doc_number] => 07535267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Output circuit and operational amplifier' [patent_app_type] => utility [patent_app_number] => 11/016946 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4093 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535267.pdf [firstpage_image] =>[orig_patent_app_number] => 11016946 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/016946
Output circuit and operational amplifier Dec 20, 2004 Issued
Array ( [id] => 6942957 [patent_doc_number] => 20050195005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Slew rate controlled output driver for use in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/020771 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195005.pdf [firstpage_image] =>[orig_patent_app_number] => 11020771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020771
Slew rate controlled output driver for use in semiconductor device Dec 20, 2004 Issued
Array ( [id] => 886481 [patent_doc_number] => 07352230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Internal voltage trimming circuit for use in semiconductor memory device and method thereof' [patent_app_type] => utility [patent_app_number] => 11/015474 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2302 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352230.pdf [firstpage_image] =>[orig_patent_app_number] => 11015474 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015474
Internal voltage trimming circuit for use in semiconductor memory device and method thereof Dec 19, 2004 Issued
Array ( [id] => 721806 [patent_doc_number] => 07049877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Switched level-shift circuit' [patent_app_type] => utility [patent_app_number] => 11/017425 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4095 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049877.pdf [firstpage_image] =>[orig_patent_app_number] => 11017425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017425
Switched level-shift circuit Dec 19, 2004 Issued
Array ( [id] => 6994556 [patent_doc_number] => 20050134334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Reset circuit' [patent_app_type] => utility [patent_app_number] => 11/012712 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3512 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134334.pdf [firstpage_image] =>[orig_patent_app_number] => 11012712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012712
Reset circuit Dec 14, 2004 Issued
Array ( [id] => 7108980 [patent_doc_number] => 20050206433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Apparatus for transferring various direct current voltage levels to digital output voltage levels' [patent_app_type] => utility [patent_app_number] => 11/010391 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3626 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206433.pdf [firstpage_image] =>[orig_patent_app_number] => 11010391 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010391
Apparatus for transferring various direct current voltage levels to digital output voltage levels Dec 13, 2004 Abandoned
Array ( [id] => 821054 [patent_doc_number] => 07408389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Output circuit with signal level shift' [patent_app_type] => utility [patent_app_number] => 11/000081 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4264 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408389.pdf [firstpage_image] =>[orig_patent_app_number] => 11000081 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000081
Output circuit with signal level shift Nov 30, 2004 Issued
Array ( [id] => 5774801 [patent_doc_number] => 20060103441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Digital duty cycle corrector' [patent_app_type] => utility [patent_app_number] => 10/988454 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103441.pdf [firstpage_image] =>[orig_patent_app_number] => 10988454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988454
Digital duty cycle corrector Nov 11, 2004 Issued
10/987278 Level shifter Nov 11, 2004 Abandoned
Array ( [id] => 7108961 [patent_doc_number] => 20050206414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Controlled slope voltage ramp generator' [patent_app_type] => utility [patent_app_number] => 10/989097 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2713 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206414.pdf [firstpage_image] =>[orig_patent_app_number] => 10989097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989097
Controlled slope voltage ramp generator Nov 11, 2004 Issued
Array ( [id] => 7095517 [patent_doc_number] => 20050127975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Spread spectrum clock generating circuit' [patent_app_type] => utility [patent_app_number] => 10/985953 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2400 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127975.pdf [firstpage_image] =>[orig_patent_app_number] => 10985953 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985953
Spread spectrum clock generating circuit Nov 11, 2004 Issued
Array ( [id] => 5863633 [patent_doc_number] => 20060097763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Delay locked loop having internal test path' [patent_app_type] => utility [patent_app_number] => 10/985289 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4745 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097763.pdf [firstpage_image] =>[orig_patent_app_number] => 10985289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985289
Delay locked loop having internal test path Nov 9, 2004 Issued
Array ( [id] => 6916047 [patent_doc_number] => 20050093608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'DC-offset transient response cancel system' [patent_app_type] => utility [patent_app_number] => 10/973915 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3603 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093608.pdf [firstpage_image] =>[orig_patent_app_number] => 10973915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973915
DC-offset transient response cancel system Oct 26, 2004 Issued
Array ( [id] => 5741634 [patent_doc_number] => 20060087358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'LEVEL SHIFT CIRCUITS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 10/973018 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2121 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087358.pdf [firstpage_image] =>[orig_patent_app_number] => 10973018 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973018
Level shift circuits and related methods Oct 24, 2004 Issued
Array ( [id] => 7155572 [patent_doc_number] => 20050083094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Timing signal generation apparatus' [patent_app_type] => utility [patent_app_number] => 10/963246 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2300 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083094.pdf [firstpage_image] =>[orig_patent_app_number] => 10963246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/963246
Signal generation apparatus for supplying timing signal to solid state device Oct 11, 2004 Issued
Array ( [id] => 5713628 [patent_doc_number] => 20060076991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'LOW POWER HIGH FREQUENCY PHASE DETECTOR' [patent_app_type] => utility [patent_app_number] => 10/960608 [patent_app_country] => US [patent_app_date] => 2004-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5580 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076991.pdf [firstpage_image] =>[orig_patent_app_number] => 10960608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960608
Low power high frequency phase detector Oct 6, 2004 Issued
Array ( [id] => 7222480 [patent_doc_number] => 20050077926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Switch circuit for switching clock signals' [patent_app_type] => utility [patent_app_number] => 10/958364 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2228 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077926.pdf [firstpage_image] =>[orig_patent_app_number] => 10958364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/958364
Method of using a switch circuit in-phase switching clock signals Oct 5, 2004 Issued
Array ( [id] => 5635416 [patent_doc_number] => 20060066389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Variable gain charge pump controller' [patent_app_type] => utility [patent_app_number] => 10/955755 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1783 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066389.pdf [firstpage_image] =>[orig_patent_app_number] => 10955755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/955755
Variable gain charge pump controller Sep 28, 2004 Abandoned
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