
Khareem E. Almo
Examiner (ID: 12419, Phone: (571)272-5524 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2842, 2849, 2816 |
| Total Applications | 1041 |
| Issued Applications | 887 |
| Pending Applications | 71 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7222635
[patent_doc_number] => 20050077948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Output circuit'
[patent_app_type] => utility
[patent_app_number] => 10/948439
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3862
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077948.pdf
[firstpage_image] =>[orig_patent_app_number] => 10948439
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/948439 | Output circuit | Sep 23, 2004 | Issued |
Array
(
[id] => 523790
[patent_doc_number] => 07190197
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-13
[patent_title] => 'Clock phase detector for noise management'
[patent_app_type] => utility
[patent_app_number] => 10/949970
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 3762
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190197.pdf
[firstpage_image] =>[orig_patent_app_number] => 10949970
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/949970 | Clock phase detector for noise management | Sep 23, 2004 | Issued |
Array
(
[id] => 114349
[patent_doc_number] => 07714641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Voltage regulator arrangement'
[patent_app_type] => utility
[patent_app_number] => 10/946579
[patent_app_country] => US
[patent_app_date] => 2004-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3320
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/714/07714641.pdf
[firstpage_image] =>[orig_patent_app_number] => 10946579
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/946579 | Voltage regulator arrangement | Sep 19, 2004 | Issued |
Array
(
[id] => 492329
[patent_doc_number] => 07215170
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-08
[patent_title] => 'Low voltage logic circuit with set and/or reset functionality'
[patent_app_type] => utility
[patent_app_number] => 10/941753
[patent_app_country] => US
[patent_app_date] => 2004-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 11620
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/215/07215170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10941753
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/941753 | Low voltage logic circuit with set and/or reset functionality | Sep 14, 2004 | Issued |
Array
(
[id] => 717642
[patent_doc_number] => 07053667
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-30
[patent_title] => 'Single wire digital interface'
[patent_app_type] => utility
[patent_app_number] => 10/937926
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3013
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/053/07053667.pdf
[firstpage_image] =>[orig_patent_app_number] => 10937926
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/937926 | Single wire digital interface | Sep 9, 2004 | Issued |
Array
(
[id] => 370304
[patent_doc_number] => 07477079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Single ended switched capacitor circuit'
[patent_app_type] => utility
[patent_app_number] => 10/938002
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 2447
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/477/07477079.pdf
[firstpage_image] =>[orig_patent_app_number] => 10938002
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938002 | Single ended switched capacitor circuit | Sep 9, 2004 | Issued |
Array
(
[id] => 7149035
[patent_doc_number] => 20050024108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'
[patent_app_type] => utility
[patent_app_number] => 10/932942
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5061
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20050024108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932942 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops | Sep 1, 2004 | Issued |
Array
(
[id] => 7149035
[patent_doc_number] => 20050024108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'
[patent_app_type] => utility
[patent_app_number] => 10/932942
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5061
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20050024108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932942 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops | Sep 1, 2004 | Issued |
Array
(
[id] => 7149035
[patent_doc_number] => 20050024108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'
[patent_app_type] => utility
[patent_app_number] => 10/932942
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5061
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20050024108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932942 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops | Sep 1, 2004 | Issued |
Array
(
[id] => 7149035
[patent_doc_number] => 20050024108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'
[patent_app_type] => utility
[patent_app_number] => 10/932942
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5061
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20050024108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932942 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops | Sep 1, 2004 | Issued |
Array
(
[id] => 5899019
[patent_doc_number] => 20060044022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'EDGE DETECTOR AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 10/926235
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5227
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20060044022.pdf
[firstpage_image] =>[orig_patent_app_number] => 10926235
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/926235 | Edge detector and method | Aug 24, 2004 | Issued |
Array
(
[id] => 7002941
[patent_doc_number] => 20050168254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'HIGH RESOLUTION PHASE LOCKED LOOP'
[patent_app_type] => utility
[patent_app_number] => 10/710894
[patent_app_country] => US
[patent_app_date] => 2004-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2070
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20050168254.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710894
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710894 | High resolution phase locked loop | Aug 10, 2004 | Issued |
Array
(
[id] => 803768
[patent_doc_number] => 07423475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Providing optimal supply voltage to integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/710861
[patent_app_country] => US
[patent_app_date] => 2004-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 7770
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/423/07423475.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710861
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710861 | Providing optimal supply voltage to integrated circuits | Aug 8, 2004 | Issued |
Array
(
[id] => 7108974
[patent_doc_number] => 20050206427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 10/912069
[patent_app_country] => US
[patent_app_date] => 2004-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4047
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20050206427.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912069
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912069 | Semiconductor integrated circuit device | Aug 5, 2004 | Abandoned |
Array
(
[id] => 34030
[patent_doc_number] => 07791397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'High speed digital level shifter'
[patent_app_type] => utility
[patent_app_number] => 10/901700
[patent_app_country] => US
[patent_app_date] => 2004-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4551
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/791/07791397.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901700
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901700 | High speed digital level shifter | Jul 27, 2004 | Issued |
Array
(
[id] => 6989182
[patent_doc_number] => 20050088219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit'
[patent_app_type] => utility
[patent_app_number] => 10/888718
[patent_app_country] => US
[patent_app_date] => 2004-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4284
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20050088219.pdf
[firstpage_image] =>[orig_patent_app_number] => 10888718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/888718 | Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit | Jul 8, 2004 | Issued |
Array
(
[id] => 709161
[patent_doc_number] => 07061297
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Input buffer circuit, and semiconductor apparatus having the same'
[patent_app_type] => utility
[patent_app_number] => 10/886626
[patent_app_country] => US
[patent_app_date] => 2004-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4006
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/061/07061297.pdf
[firstpage_image] =>[orig_patent_app_number] => 10886626
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/886626 | Input buffer circuit, and semiconductor apparatus having the same | Jul 8, 2004 | Issued |
Array
(
[id] => 7087058
[patent_doc_number] => 20050007170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Asynchronous control circuit and semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 10/885018
[patent_app_country] => US
[patent_app_date] => 2004-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12665
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20050007170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10885018
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/885018 | Asynchronous control circuit and semiconductor integrated circuit device | Jul 6, 2004 | Abandoned |
Array
(
[id] => 760044
[patent_doc_number] => 07015728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-03-21
[patent_title] => 'High voltage floating current sense amplifier'
[patent_app_type] => utility
[patent_app_number] => 10/886368
[patent_app_country] => US
[patent_app_date] => 2004-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5929
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/015/07015728.pdf
[firstpage_image] =>[orig_patent_app_number] => 10886368
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/886368 | High voltage floating current sense amplifier | Jul 6, 2004 | Issued |
Array
(
[id] => 7114779
[patent_doc_number] => 20050068080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Timing-flexible flip-flop element'
[patent_app_type] => utility
[patent_app_number] => 10/880492
[patent_app_country] => US
[patent_app_date] => 2004-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2692
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20050068080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10880492
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/880492 | Timing-flexible flip-flop element | Jun 30, 2004 | Abandoned |