Search

Khareem E. Almo

Examiner (ID: 13774, Phone: (571)272-5524 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2849, 2836, 2816, 2842
Total Applications
1065
Issued Applications
903
Pending Applications
64
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7114779 [patent_doc_number] => 20050068080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Timing-flexible flip-flop element' [patent_app_type] => utility [patent_app_number] => 10/880492 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068080.pdf [firstpage_image] =>[orig_patent_app_number] => 10880492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880492
Timing-flexible flip-flop element Jun 30, 2004 Abandoned
Array ( [id] => 6975931 [patent_doc_number] => 20050285646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Closed-loop control of driver slew rate' [patent_app_type] => utility [patent_app_number] => 10/881003 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6068 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285646.pdf [firstpage_image] =>[orig_patent_app_number] => 10881003 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881003
Closed-loop control of driver slew rate Jun 28, 2004 Issued
Array ( [id] => 542036 [patent_doc_number] => 07176737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs' [patent_app_type] => utility [patent_app_number] => 10/876730 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6628 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176737.pdf [firstpage_image] =>[orig_patent_app_number] => 10876730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876730
Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs Jun 24, 2004 Issued
Array ( [id] => 7408306 [patent_doc_number] => 20040263220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Voltage-controlled switch control device' [patent_app_type] => new [patent_app_number] => 10/877747 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3897 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263220.pdf [firstpage_image] =>[orig_patent_app_number] => 10877747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877747
Voltage-controlled switch control device Jun 24, 2004 Abandoned
Array ( [id] => 857735 [patent_doc_number] => 07375565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Delay locked loop in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/877071 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 6776 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375565.pdf [firstpage_image] =>[orig_patent_app_number] => 10877071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877071
Delay locked loop in semiconductor memory device Jun 24, 2004 Issued
Array ( [id] => 726334 [patent_doc_number] => 07046047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Clock switching circuit' [patent_app_type] => utility [patent_app_number] => 10/875220 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4391 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046047.pdf [firstpage_image] =>[orig_patent_app_number] => 10875220 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875220
Clock switching circuit Jun 24, 2004 Issued
Array ( [id] => 8166183 [patent_doc_number] => 08174291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-08 [patent_title] => 'Buffer circuit with improved duty cycle distortion and method of using the same' [patent_app_type] => utility [patent_app_number] => 10/875888 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7130 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174291.pdf [firstpage_image] =>[orig_patent_app_number] => 10875888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875888
Buffer circuit with improved duty cycle distortion and method of using the same Jun 23, 2004 Issued
Array ( [id] => 7155571 [patent_doc_number] => 20050083093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Flip-flop' [patent_app_type] => utility [patent_app_number] => 10/873178 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083093.pdf [firstpage_image] =>[orig_patent_app_number] => 10873178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873178
Flip-flop Jun 22, 2004 Abandoned
Array ( [id] => 752629 [patent_doc_number] => 07023255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Latch with data jitter free clock load' [patent_app_type] => utility [patent_app_number] => 10/874513 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023255.pdf [firstpage_image] =>[orig_patent_app_number] => 10874513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874513
Latch with data jitter free clock load Jun 22, 2004 Issued
Array ( [id] => 793542 [patent_doc_number] => 06982588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Inverse function method for semiconductor mixer linearity enhancement' [patent_app_type] => utility [patent_app_number] => 10/869680 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1128 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982588.pdf [firstpage_image] =>[orig_patent_app_number] => 10869680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869680
Inverse function method for semiconductor mixer linearity enhancement Jun 15, 2004 Issued
Array ( [id] => 7054263 [patent_doc_number] => 20050275435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Comparator using differential amplifier with reduced current consumption' [patent_app_type] => utility [patent_app_number] => 10/867896 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275435.pdf [firstpage_image] =>[orig_patent_app_number] => 10867896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867896
Comparator using differential amplifier with reduced current consumption Jun 14, 2004 Issued
Array ( [id] => 7054275 [patent_doc_number] => 20050275447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'One-pin automatic tuning of MOSFET resistors' [patent_app_type] => utility [patent_app_number] => 10/865605 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3471 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275447.pdf [firstpage_image] =>[orig_patent_app_number] => 10865605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865605
One-pin automatic tuning of MOSFET resistors Jun 9, 2004 Issued
Array ( [id] => 7252259 [patent_doc_number] => 20040239400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Integrated circuit and method for operating the integrated circuit' [patent_app_type] => new [patent_app_number] => 10/857616 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6846 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20040239400.pdf [firstpage_image] =>[orig_patent_app_number] => 10857616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857616
Integrated circuit and method for operating the integrated circuit May 26, 2004 Issued
Array ( [id] => 5202899 [patent_doc_number] => 20070024378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Voltage shift control circuit for pll' [patent_app_type] => utility [patent_app_number] => 10/556647 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3937 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20070024378.pdf [firstpage_image] =>[orig_patent_app_number] => 10556647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/556647
Voltage shift control circuit for PLL May 16, 2004 Issued
Array ( [id] => 7324100 [patent_doc_number] => 20040251946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Analog delay circuit' [patent_app_type] => new [patent_app_number] => 10/494656 [patent_app_country] => US [patent_app_date] => 2004-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3416 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251946.pdf [firstpage_image] =>[orig_patent_app_number] => 10494656 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/494656
Analog delay circuit May 3, 2004 Abandoned
Array ( [id] => 696671 [patent_doc_number] => 07071746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Variable delay circuit' [patent_app_type] => utility [patent_app_number] => 10/835098 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11646 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071746.pdf [firstpage_image] =>[orig_patent_app_number] => 10835098 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835098
Variable delay circuit Apr 28, 2004 Issued
Array ( [id] => 709144 [patent_doc_number] => 07061285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Clock doubler' [patent_app_type] => utility [patent_app_number] => 10/826197 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5040 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061285.pdf [firstpage_image] =>[orig_patent_app_number] => 10826197 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/826197
Clock doubler Apr 14, 2004 Issued
Array ( [id] => 931536 [patent_doc_number] => 06980042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Delay line synchronizer apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/819366 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8132 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/980/06980042.pdf [firstpage_image] =>[orig_patent_app_number] => 10819366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819366
Delay line synchronizer apparatus and method Apr 4, 2004 Issued
Array ( [id] => 6994576 [patent_doc_number] => 20050134354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Circuit arrangement for generating a digital clock signal' [patent_app_type] => utility [patent_app_number] => 10/818928 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134354.pdf [firstpage_image] =>[orig_patent_app_number] => 10818928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/818928
Circuit arrangement for generating a digital clock signal Apr 4, 2004 Issued
Array ( [id] => 7292449 [patent_doc_number] => 20040212422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Internal voltage generating circuit for semiconductor device' [patent_app_type] => new [patent_app_number] => 10/799783 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4146 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212422.pdf [firstpage_image] =>[orig_patent_app_number] => 10799783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799783
Internal voltage generating circuit for semiconductor device Mar 11, 2004 Abandoned
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