Search

Khawaja Anwar

Examiner (ID: 3466)

Most Active Art Unit
2912
Art Unit(s)
2964, 2912
Total Applications
2868
Issued Applications
2722
Pending Applications
18
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3454367 [patent_doc_number] => 05430864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size' [patent_app_type] => 1 [patent_app_number] => 8/321459 [patent_app_country] => US [patent_app_date] => 1994-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5241 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430864.pdf [firstpage_image] =>[orig_patent_app_number] => 321459 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/321459
Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size Oct 10, 1994 Issued
Array ( [id] => 3420297 [patent_doc_number] => 05438682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Data processing system for rewriting parallel processor output data using a sequential processor' [patent_app_type] => 1 [patent_app_number] => 8/297110 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 6705 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438682.pdf [firstpage_image] =>[orig_patent_app_number] => 297110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/297110
Data processing system for rewriting parallel processor output data using a sequential processor Aug 25, 1994 Issued
Array ( [id] => 3437678 [patent_doc_number] => 05404467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability' [patent_app_type] => 1 [patent_app_number] => 8/261318 [patent_app_country] => US [patent_app_date] => 1994-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 11277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404467.pdf [firstpage_image] =>[orig_patent_app_number] => 261318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261318
CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability Jun 15, 1994 Issued
Array ( [id] => 3433469 [patent_doc_number] => 05390320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile' [patent_app_type] => 1 [patent_app_number] => 8/237317 [patent_app_country] => US [patent_app_date] => 1994-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10658 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390320.pdf [firstpage_image] =>[orig_patent_app_number] => 237317 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237317
Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile May 2, 1994 Issued
Array ( [id] => 3458171 [patent_doc_number] => 05420992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Backward-compatible computer architecture with extended word size and address space' [patent_app_type] => 1 [patent_app_number] => 8/223388 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 12913 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420992.pdf [firstpage_image] =>[orig_patent_app_number] => 223388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223388
Backward-compatible computer architecture with extended word size and address space Apr 4, 1994 Issued
Array ( [id] => 3435450 [patent_doc_number] => 05423014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Instruction fetch unit with early instruction fetch mechanism' [patent_app_type] => 1 [patent_app_number] => 8/202710 [patent_app_country] => US [patent_app_date] => 1994-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9148 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/423/05423014.pdf [firstpage_image] =>[orig_patent_app_number] => 202710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202710
Instruction fetch unit with early instruction fetch mechanism Feb 23, 1994 Issued
Array ( [id] => 3453244 [patent_doc_number] => 05398321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Microcode generation for a scalable compound instruction set machine' [patent_app_type] => 1 [patent_app_number] => 8/184401 [patent_app_country] => US [patent_app_date] => 1994-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9247 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398321.pdf [firstpage_image] =>[orig_patent_app_number] => 184401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/184401
Microcode generation for a scalable compound instruction set machine Jan 20, 1994 Issued
Array ( [id] => 3439130 [patent_doc_number] => 05404563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Scheduling normally interchangeable facilities in multiprocessor computer systems' [patent_app_type] => 1 [patent_app_number] => 8/181379 [patent_app_country] => US [patent_app_date] => 1994-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9069 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404563.pdf [firstpage_image] =>[orig_patent_app_number] => 181379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/181379
Scheduling normally interchangeable facilities in multiprocessor computer systems Jan 13, 1994 Issued
08/171970 DATA PROCESSING DEVICE FOR VARIABLE WORD LENGTH INSTRUCTION SYSTEM HAVING SHORT INSTRUCTION EXECUTION TIME AND SMALL OCCUPANCY AREA Dec 22, 1993 Abandoned
08/151772 PROCESSING METHOD BY WHICH CONTINUOUS OPERATION OF COMMUNICATION CONTROL PROGRAM IS OBTAINED Nov 14, 1993 Abandoned
08/145902 SPECULATIVE INSTRUCTION QUEUE AND METHOD THEREFOR PARTICULARLY SUITABLE FOR VARIABLE BYTE-LENGTH INSTRUCTIONS Oct 28, 1993 Abandoned
08/146433 METHOD AND APPARATUS FOR EXTENDING COMPUTER ARCHITECTURE FROM THIRTY-TWO TO SIXTY-FOUR BITS Oct 28, 1993 Abandoned
Array ( [id] => 3069370 [patent_doc_number] => 05357626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Processing system for providing an in circuit emulator with processor internal state' [patent_app_type] => 1 [patent_app_number] => 8/139607 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5035 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357626.pdf [firstpage_image] =>[orig_patent_app_number] => 139607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/139607
Processing system for providing an in circuit emulator with processor internal state Oct 19, 1993 Issued
08/130535 PIPELINED COMPUTER WITH HALF MACHINE CYCLE ALTERNATING WRITE CONTROL FOR AVOIDING USAGE CONFLICTS IN GENERAL REGISTERS Sep 30, 1993 Abandoned
08/114236 DATA PROCESSING SYSTEM Aug 31, 1993 Abandoned
Array ( [id] => 3050673 [patent_doc_number] => 05301333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Tree structured variable priority arbitration implementing a round-robin scheduling policy' [patent_app_type] => 1 [patent_app_number] => 8/113588 [patent_app_country] => US [patent_app_date] => 1993-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4427 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301333.pdf [firstpage_image] =>[orig_patent_app_number] => 113588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/113588
Tree structured variable priority arbitration implementing a round-robin scheduling policy Aug 26, 1993 Issued
Array ( [id] => 3064814 [patent_doc_number] => 05325512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Circuit emulator' [patent_app_type] => 1 [patent_app_number] => 8/090333 [patent_app_country] => US [patent_app_date] => 1993-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4003 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325512.pdf [firstpage_image] =>[orig_patent_app_number] => 090333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/090333
Circuit emulator Jul 11, 1993 Issued
Array ( [id] => 3058865 [patent_doc_number] => 05287487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Predictive caching method and apparatus for generating a predicted address for a frame buffer' [patent_app_type] => 1 [patent_app_number] => 8/074703 [patent_app_country] => US [patent_app_date] => 1993-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5307 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287487.pdf [firstpage_image] =>[orig_patent_app_number] => 074703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/074703
Predictive caching method and apparatus for generating a predicted address for a frame buffer Jun 8, 1993 Issued
Array ( [id] => 3053209 [patent_doc_number] => 05377337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Method and means for enabling virtual addressing control by software users over a hardware page transfer control entity' [patent_app_type] => 1 [patent_app_number] => 8/073815 [patent_app_country] => US [patent_app_date] => 1993-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 15226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 598 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377337.pdf [firstpage_image] =>[orig_patent_app_number] => 073815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/073815
Method and means for enabling virtual addressing control by software users over a hardware page transfer control entity Jun 7, 1993 Issued
Array ( [id] => 3435409 [patent_doc_number] => 05404321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Computer system and method for modifying and enhancing the built-in programs of a computer' [patent_app_type] => 1 [patent_app_number] => 8/064654 [patent_app_country] => US [patent_app_date] => 1993-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404321.pdf [firstpage_image] =>[orig_patent_app_number] => 064654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/064654
Computer system and method for modifying and enhancing the built-in programs of a computer May 20, 1993 Issued
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