| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1995-07-04
[patent_title] => 'Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size'
[patent_app_type] => 1
[patent_app_number] => 8/321459
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Array
(
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[patent_doc_number] => 05438682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Data processing system for rewriting parallel processor output data using a sequential processor'
[patent_app_type] => 1
[patent_app_number] => 8/297110
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[firstpage_image] =>[orig_patent_app_number] => 297110
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/297110 | Data processing system for rewriting parallel processor output data using a sequential processor | Aug 25, 1994 | Issued |
Array
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[id] => 3437678
[patent_doc_number] => 05404467
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability'
[patent_app_type] => 1
[patent_app_number] => 8/261318
[patent_app_country] => US
[patent_app_date] => 1994-06-16
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[firstpage_image] =>[orig_patent_app_number] => 261318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/261318 | CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability | Jun 15, 1994 | Issued |
Array
(
[id] => 3433469
[patent_doc_number] => 05390320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile'
[patent_app_type] => 1
[patent_app_number] => 8/237317
[patent_app_country] => US
[patent_app_date] => 1994-05-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/237317 | Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile | May 2, 1994 | Issued |
Array
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[id] => 3458171
[patent_doc_number] => 05420992
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Backward-compatible computer architecture with extended word size and address space'
[patent_app_type] => 1
[patent_app_number] => 8/223388
[patent_app_country] => US
[patent_app_date] => 1994-04-05
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[pdf_file] => patents/05/420/05420992.pdf
[firstpage_image] =>[orig_patent_app_number] => 223388
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223388 | Backward-compatible computer architecture with extended word size and address space | Apr 4, 1994 | Issued |
Array
(
[id] => 3435450
[patent_doc_number] => 05423014
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[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Instruction fetch unit with early instruction fetch mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/202710
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[firstpage_image] =>[orig_patent_app_number] => 202710
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/202710 | Instruction fetch unit with early instruction fetch mechanism | Feb 23, 1994 | Issued |
Array
(
[id] => 3453244
[patent_doc_number] => 05398321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Microcode generation for a scalable compound instruction set machine'
[patent_app_type] => 1
[patent_app_number] => 8/184401
[patent_app_country] => US
[patent_app_date] => 1994-01-21
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[pdf_file] => patents/05/398/05398321.pdf
[firstpage_image] =>[orig_patent_app_number] => 184401
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/184401 | Microcode generation for a scalable compound instruction set machine | Jan 20, 1994 | Issued |
Array
(
[id] => 3439130
[patent_doc_number] => 05404563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Scheduling normally interchangeable facilities in multiprocessor computer systems'
[patent_app_type] => 1
[patent_app_number] => 8/181379
[patent_app_country] => US
[patent_app_date] => 1994-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/404/05404563.pdf
[firstpage_image] =>[orig_patent_app_number] => 181379
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/181379 | Scheduling normally interchangeable facilities in multiprocessor computer systems | Jan 13, 1994 | Issued |
| 08/171970 | DATA PROCESSING DEVICE FOR VARIABLE WORD LENGTH INSTRUCTION SYSTEM HAVING SHORT INSTRUCTION EXECUTION TIME AND SMALL OCCUPANCY AREA | Dec 22, 1993 | Abandoned |
| 08/151772 | PROCESSING METHOD BY WHICH CONTINUOUS OPERATION OF COMMUNICATION CONTROL PROGRAM IS OBTAINED | Nov 14, 1993 | Abandoned |
| 08/145902 | SPECULATIVE INSTRUCTION QUEUE AND METHOD THEREFOR PARTICULARLY SUITABLE FOR VARIABLE BYTE-LENGTH INSTRUCTIONS | Oct 28, 1993 | Abandoned |
| 08/146433 | METHOD AND APPARATUS FOR EXTENDING COMPUTER ARCHITECTURE FROM THIRTY-TWO TO SIXTY-FOUR BITS | Oct 28, 1993 | Abandoned |
Array
(
[id] => 3069370
[patent_doc_number] => 05357626
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Processing system for providing an in circuit emulator with processor internal state'
[patent_app_type] => 1
[patent_app_number] => 8/139607
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[patent_app_date] => 1993-10-20
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[firstpage_image] =>[orig_patent_app_number] => 139607
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/139607 | Processing system for providing an in circuit emulator with processor internal state | Oct 19, 1993 | Issued |
| 08/130535 | PIPELINED COMPUTER WITH HALF MACHINE CYCLE ALTERNATING WRITE CONTROL FOR AVOIDING USAGE CONFLICTS IN GENERAL REGISTERS | Sep 30, 1993 | Abandoned |
| 08/114236 | DATA PROCESSING SYSTEM | Aug 31, 1993 | Abandoned |
Array
(
[id] => 3050673
[patent_doc_number] => 05301333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Tree structured variable priority arbitration implementing a round-robin scheduling policy'
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[pdf_file] => patents/05/301/05301333.pdf
[firstpage_image] =>[orig_patent_app_number] => 113588
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113588 | Tree structured variable priority arbitration implementing a round-robin scheduling policy | Aug 26, 1993 | Issued |
Array
(
[id] => 3064814
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[patent_kind] => NA
[patent_issue_date] => 1994-06-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/090333 | Circuit emulator | Jul 11, 1993 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/074703 | Predictive caching method and apparatus for generating a predicted address for a frame buffer | Jun 8, 1993 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/073815 | Method and means for enabling virtual addressing control by software users over a hardware page transfer control entity | Jun 7, 1993 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/064654 | Computer system and method for modifying and enhancing the built-in programs of a computer | May 20, 1993 | Issued |