Search

Khiem D Nguyen

Examiner (ID: 4456, Phone: (571)270-3941 , Office: P/2842 )

Most Active Art Unit
2823
Art Unit(s)
2892, 2842, 2843, 4146, 2823, 2817
Total Applications
2760
Issued Applications
2233
Pending Applications
206
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19843184 [patent_doc_number] => 12255591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Temperature compensation bias circuit and power amplifier [patent_app_type] => utility [patent_app_number] => 18/806715 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4637 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806715
Temperature compensation bias circuit and power amplifier Aug 15, 2024 Issued
Array ( [id] => 19484160 [patent_doc_number] => 20240332202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/735194 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735194 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735194
PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE SAME Jun 5, 2024 Pending
Array ( [id] => 19467991 [patent_doc_number] => 20240321661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKAGES WITH MULTIPLE ENCAPSULATED SUBSTRATE BLOCKS [patent_app_type] => utility [patent_app_number] => 18/679091 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679091
PACKAGES WITH MULTIPLE ENCAPSULATED SUBSTRATE BLOCKS May 29, 2024 Pending
Array ( [id] => 20111539 [patent_doc_number] => 12362275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Method of fabricating package structure including a plurality of antenna patterns [patent_app_type] => utility [patent_app_number] => 18/672001 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672001
Method of fabricating package structure including a plurality of antenna patterns May 22, 2024 Issued
Array ( [id] => 19421007 [patent_doc_number] => 20240297131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => METHODS OF FORMING SEMICONDUCTOR PACKAGES HAVING A DIE WITH AN ENCAPSULANT [patent_app_type] => utility [patent_app_number] => 18/663697 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663697
METHODS OF FORMING SEMICONDUCTOR PACKAGES HAVING A DIE WITH AN ENCAPSULANT May 13, 2024 Pending
Array ( [id] => 20404771 [patent_doc_number] => 12494755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Apparatus and method of power management using envelope stacking [patent_app_type] => utility [patent_app_number] => 18/661761 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661761
Apparatus and method of power management using envelope stacking May 12, 2024 Issued
Array ( [id] => 19407943 [patent_doc_number] => 20240291454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => POWER RECONFIGURABLE POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/659409 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659409
POWER RECONFIGURABLE POWER AMPLIFIER May 8, 2024 Pending
Array ( [id] => 20346022 [patent_doc_number] => 12469757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Package structure including a die having a taper-shaped die connector [patent_app_type] => utility [patent_app_number] => 18/652779 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 103 [patent_no_of_words] => 16562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652779
Package structure including a die having a taper-shaped die connector Apr 30, 2024 Issued
Array ( [id] => 20389339 [patent_doc_number] => 12489074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Package structure having a device inside a molding member and method of forming the package structure [patent_app_type] => utility [patent_app_number] => 18/650143 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 46 [patent_no_of_words] => 4425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650143
Package structure having a device inside a molding member and method of forming the package structure Apr 29, 2024 Issued
Array ( [id] => 19392803 [patent_doc_number] => 20240282673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 18/643322 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643322
METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF Apr 22, 2024 Pending
Array ( [id] => 19384109 [patent_doc_number] => 20240273979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHOD FOR OPERATING A GAMING DEVICE THAT DISPLAYS SYMBOLS [patent_app_type] => utility [patent_app_number] => 18/643541 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643541
METHOD FOR OPERATING A GAMING DEVICE THAT DISPLAYS SYMBOLS Apr 22, 2024 Pending
Array ( [id] => 19349242 [patent_doc_number] => 20240258206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network [patent_app_type] => utility [patent_app_number] => 18/635613 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635613
Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network Apr 14, 2024 Pending
Array ( [id] => 20175932 [patent_doc_number] => 12394688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Superconducting device including set of circuits having different operational temperature requirements with multiple thermal sinks and multiple ground planes [patent_app_type] => utility [patent_app_number] => 18/630530 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630530
Superconducting device including set of circuits having different operational temperature requirements with multiple thermal sinks and multiple ground planes Apr 8, 2024 Issued
Array ( [id] => 19393543 [patent_doc_number] => 20240283413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ENHANCED AMPLIFIER TOPOLOGY IN AN ANALOG FRONT END (AFE) [patent_app_type] => utility [patent_app_number] => 18/625276 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625276
ENHANCED AMPLIFIER TOPOLOGY IN AN ANALOG FRONT END (AFE) Apr 2, 2024 Pending
Array ( [id] => 19385468 [patent_doc_number] => 20240275338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHODS RELATED TO POWER AMPLIFICATION SYSTEMS WITH ADJUSTABLE COMMON BASE BIAS [patent_app_type] => utility [patent_app_number] => 18/609940 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609940
Methods related to power amplification systems with adjustable common base bias Mar 18, 2024 Issued
Array ( [id] => 19393540 [patent_doc_number] => 20240283410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Systems and Methods for Optimizing Amplifier Operations [patent_app_type] => utility [patent_app_number] => 18/600732 [patent_app_country] => US [patent_app_date] => 2024-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600732
Systems and methods for optimizing amplifier operations Mar 9, 2024 Issued
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