Search

Khiem D. Nguyen

Examiner (ID: 4456)

Most Active Art Unit
2823
Art Unit(s)
2892, 2842, 2843, 4146, 2823, 2817
Total Applications
2760
Issued Applications
2233
Pending Applications
206
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20274878 [patent_doc_number] => 12444663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/443338 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 1047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443338
Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof Feb 15, 2024 Issued
Array ( [id] => 20267125 [patent_doc_number] => 12438124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor package with routing patch and method of fabricating the semiconductor package [patent_app_type] => utility [patent_app_number] => 18/438638 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438638 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438638
Semiconductor package with routing patch and method of fabricating the semiconductor package Feb 11, 2024 Issued
Array ( [id] => 19191468 [patent_doc_number] => 20240170381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => INTERCONNECT STRUCTURES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/429708 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429708
INTERCONNECT STRUCTURES AND MANUFACTURING METHOD THEREOF Jan 31, 2024 Pending
Array ( [id] => 19972849 [patent_doc_number] => 12341474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier [patent_app_type] => utility [patent_app_number] => 18/427472 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427472
Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier Jan 29, 2024 Issued
Array ( [id] => 19972499 [patent_doc_number] => 12341120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Semiconductor chip and semiconductor device including a copper pillar and an intermediate layer [patent_app_type] => utility [patent_app_number] => 18/423463 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 6808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423463
Semiconductor chip and semiconductor device including a copper pillar and an intermediate layer Jan 25, 2024 Issued
Array ( [id] => 19766072 [patent_doc_number] => 12224376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Light-emitting display device and electronic device including a first pixel and a second pixel and an oxide semiconductor region overlapping a light-emitting region [patent_app_type] => utility [patent_app_number] => 18/417474 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 12985 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417474
Light-emitting display device and electronic device including a first pixel and a second pixel and an oxide semiconductor region overlapping a light-emitting region Jan 18, 2024 Issued
Array ( [id] => 19469090 [patent_doc_number] => 20240322760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Constant VDS1 Bias Control for Stacked Transistor Configuration [patent_app_type] => utility [patent_app_number] => 18/406724 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406724 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406724
Constant VDS1 Bias Control for Stacked Transistor Configuration Jan 7, 2024 Pending
Array ( [id] => 19130893 [patent_doc_number] => 20240136246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/403686 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403686
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jan 2, 2024 Pending
Array ( [id] => 19943708 [patent_doc_number] => 12315845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/400335 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400335
Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof Dec 28, 2023 Issued
Array ( [id] => 19741784 [patent_doc_number] => 12218637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Drain switched split amplifier with capacitor switching for noise figure and isolation improvement in split mode [patent_app_type] => utility [patent_app_number] => 18/534153 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534153
Drain switched split amplifier with capacitor switching for noise figure and isolation improvement in split mode Dec 7, 2023 Issued
Array ( [id] => 19981914 [patent_doc_number] => 12349416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures [patent_app_type] => utility [patent_app_number] => 18/528545 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528545
Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures Dec 3, 2023 Issued
Array ( [id] => 19906908 [patent_doc_number] => 12283929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Audio amplifier circuitry [patent_app_type] => utility [patent_app_number] => 18/521667 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521667
Audio amplifier circuitry Nov 27, 2023 Issued
Array ( [id] => 19741217 [patent_doc_number] => 12218062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method of fabricating a semiconductor memory device including an extension gate cutting region [patent_app_type] => utility [patent_app_number] => 18/514716 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514716
Method of fabricating a semiconductor memory device including an extension gate cutting region Nov 19, 2023 Issued
Array ( [id] => 19038451 [patent_doc_number] => 20240088266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => EPITAXIAL FIN STRUCTURES OF FINFET HAVING AN EPITAXIAL BUFFER REGION AND AN EPITAXIAL CAPPING REGION [patent_app_type] => utility [patent_app_number] => 18/511711 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511711
EPITAXIAL FIN STRUCTURES OF FINFET HAVING AN EPITAXIAL BUFFER REGION AND AN EPITAXIAL CAPPING REGION Nov 15, 2023 Pending
Array ( [id] => 19023149 [patent_doc_number] => 20240079320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => PACKAGED TRANSISTOR WITH CHANNELED DIE ATTACH MATERIALS AND PROCESS OF IMPLEMENTING THE SAME [patent_app_type] => utility [patent_app_number] => 18/505197 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505197 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505197
PACKAGED TRANSISTOR WITH CHANNELED DIE ATTACH MATERIALS AND PROCESS OF IMPLEMENTING THE SAME Nov 8, 2023 Pending
Array ( [id] => 19147196 [patent_doc_number] => 20240146249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => Power Amplifier Equalizer [patent_app_type] => utility [patent_app_number] => 18/503814 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503814
Power amplifier equalizer Nov 6, 2023 Issued
Array ( [id] => 19858244 [patent_doc_number] => 12261095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor package having an encapulant comprising conductive fillers and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/499964 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 14009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499964
Semiconductor package having an encapulant comprising conductive fillers and method of manufacture Oct 31, 2023 Issued
Array ( [id] => 19007910 [patent_doc_number] => 20240071981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/499242 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499242
Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer Oct 31, 2023 Issued
Array ( [id] => 19679947 [patent_doc_number] => 12191823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Parallel cascode amplifier for enhanced low-power mode efficiency [patent_app_type] => utility [patent_app_number] => 18/493287 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5598 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493287
Parallel cascode amplifier for enhanced low-power mode efficiency Oct 23, 2023 Issued
Array ( [id] => 19101063 [patent_doc_number] => 20240120291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/482849 [patent_app_country] => US [patent_app_date] => 2023-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482849
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME Oct 6, 2023 Pending
Menu