Khiem D. Nguyen

Array ( [id] => 19646617 [patent_doc_number] => 20240421137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CHIP PACKAGE UNIT, CHIP PACKAGE STACK MODULE, AND METHOD OF MANUFACTURING CHIP PACKAGE STACK MODULE [patent_app_type] => utility [patent_app_number] => 18/645411 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19392803 [patent_doc_number] => 20240282673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 18/643322 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20091010 [patent_doc_number] => 20250220946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ISOLATION STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING [patent_app_type] => utility [patent_app_number] => 18/643324 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20311995 [patent_doc_number] => 20250329624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Semiconductor Device and Method of Forming Encapsulated Interconnect Structure for Embedded Photonic Bridge Die [patent_app_type] => utility [patent_app_number] => 18/643786 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19384109 [patent_doc_number] => 20240273979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHOD FOR OPERATING A GAMING DEVICE THAT DISPLAYS SYMBOLS [patent_app_type] => utility [patent_app_number] => 18/643541 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19866339 [patent_doc_number] => 20250105125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/637328 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19349242 [patent_doc_number] => 20240258206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network [patent_app_type] => utility [patent_app_number] => 18/635613 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19837677 [patent_doc_number] => 20250089463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/633458 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19515916 [patent_doc_number] => 20240347602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE AND METHOD OF FABRICATION THEREFOR [patent_app_type] => utility [patent_app_number] => 18/632003 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20175932 [patent_doc_number] => 12394688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Superconducting device including set of circuits having different operational temperature requirements with multiple thermal sinks and multiple ground planes [patent_app_type] => utility [patent_app_number] => 18/630530 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19532589 [patent_doc_number] => 20240356491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => AMPLIFIER AND METHOD FOR CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 18/629516 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20063429 [patent_doc_number] => 20250201651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SEMICONDUCTOR PACKAGE WITH DOUBLE-SIDED THERMAL SOLUTION AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/629044 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19532603 [patent_doc_number] => 20240356505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => AMPLIFIER AND METHOD FOR CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 18/629498 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500956 [patent_doc_number] => 20240339974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => VARACTOR TUNED INPUT TRAP [patent_app_type] => utility [patent_app_number] => 18/627682 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19393543 [patent_doc_number] => 20240283413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ENHANCED AMPLIFIER TOPOLOGY IN AN ANALOG FRONT END (AFE) [patent_app_type] => utility [patent_app_number] => 18/625276 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20283739 [patent_doc_number] => 20250308981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => METHOD FOR FORMING CAULKING LAYER, METHOD OF MANUFACTURING ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/617963 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19364973 [patent_doc_number] => 20240267007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => CLASS D AMPLIFICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/616238 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20252832 [patent_doc_number] => 20250301701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INTEGRATED CIRCUIT AND SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 18/611707 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19517847 [patent_doc_number] => 20240349533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/611764 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19385468 [patent_doc_number] => 20240275338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHODS RELATED TO POWER AMPLIFICATION SYSTEMS WITH ADJUSTABLE COMMON BASE BIAS [patent_app_type] => utility [patent_app_number] => 18/609940 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609940 [rel_patent_id] =>[rel_patent_doc_number] =>)