Search

Khiem D. Nguyen

Examiner (ID: 4456)

Most Active Art Unit
2823
Art Unit(s)
2892, 2842, 2843, 4146, 2823, 2817
Total Applications
2760
Issued Applications
2233
Pending Applications
206
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20081320 [patent_doc_number] => 12355402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Wideband amplifier linearization techniques [patent_app_type] => utility [patent_app_number] => 18/469499 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469499
Wideband amplifier linearization techniques Sep 17, 2023 Issued
Array ( [id] => 19835832 [patent_doc_number] => 20250087618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/244207 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18244207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/244207
PACKAGE STRUCTURE Sep 7, 2023 Pending
Array ( [id] => 18849097 [patent_doc_number] => 20230411501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => FABRICATING TRANSISTORS WITH IMPLANTING DOPANTS AT FIRST AND SECOND DOSAGES IN THE COLLECTOR REGION TO FORM THE BASE REGION [patent_app_type] => utility [patent_app_number] => 18/242919 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/242919
FABRICATING TRANSISTORS WITH IMPLANTING DOPANTS AT FIRST AND SECOND DOSAGES IN THE COLLECTOR REGION TO FORM THE BASE REGION Sep 5, 2023 Pending
Array ( [id] => 18991272 [patent_doc_number] => 20240063241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => IMAGE SENSOR INCLUDING PATTERNED ANTIREFLECTION LAYER AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/235547 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235547
IMAGE SENSOR INCLUDING PATTERNED ANTIREFLECTION LAYER AND ELECTRONIC APPARATUS INCLUDING THE SAME Aug 17, 2023 Pending
Array ( [id] => 19590706 [patent_doc_number] => 20240388263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => WIDEBAND SWITCHING GAIN ENHANCED TUNABLE LNA ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/452467 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452467 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452467
WIDEBAND SWITCHING GAIN ENHANCED TUNABLE LNA ARCHITECTURE Aug 17, 2023 Pending
Array ( [id] => 19444587 [patent_doc_number] => 12094878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor integrated circuit device having a standard cell which includes a fin and a dummy transistor [patent_app_type] => utility [patent_app_number] => 18/450146 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4686 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450146
Semiconductor integrated circuit device having a standard cell which includes a fin and a dummy transistor Aug 14, 2023 Issued
Array ( [id] => 18975942 [patent_doc_number] => 20240056034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/448457 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448457
BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT Aug 10, 2023 Pending
Array ( [id] => 19827403 [patent_doc_number] => 12248178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Packaged device including an optical path structure aligned to an optical feature [patent_app_type] => utility [patent_app_number] => 18/447560 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 7714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447560
Packaged device including an optical path structure aligned to an optical feature Aug 9, 2023 Issued
Array ( [id] => 20244247 [patent_doc_number] => 12424579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Integrated chip including an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance [patent_app_type] => utility [patent_app_number] => 18/446571 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 6002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446571
Integrated chip including an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance Aug 8, 2023 Issued
Array ( [id] => 19672737 [patent_doc_number] => 12185532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Structure of memory device having floating gate with protruding structure [patent_app_type] => utility [patent_app_number] => 18/365243 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4087 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365243
Structure of memory device having floating gate with protruding structure Aug 3, 2023 Issued
Array ( [id] => 18812619 [patent_doc_number] => 20230386956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/363742 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363742
Manufacturing method of semiconductor package including forming cavity in circuit substrate without exposing floor plate Aug 1, 2023 Issued
Array ( [id] => 18927872 [patent_doc_number] => 20240030876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Power Amplifier Linearizer [patent_app_type] => utility [patent_app_number] => 18/361590 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361590
Power amplifier linearizer Jul 27, 2023 Issued
Array ( [id] => 18944353 [patent_doc_number] => 20240039492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DIFFERENTIAL AMPLIFIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/359116 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359116
DIFFERENTIAL AMPLIFIER CIRCUIT Jul 25, 2023 Pending
Array ( [id] => 18789695 [patent_doc_number] => 20230378408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => LIGHT EMITTING DEVICE INCLUDING FIRST REFLECTING LAYER AND SECOND REFLECTING LAYER [patent_app_type] => utility [patent_app_number] => 18/358657 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358657
Light emitting device including first reflecting layer and second reflecting layer Jul 24, 2023 Issued
Array ( [id] => 18774444 [patent_doc_number] => 20230369275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD AND STRUCTURE TO CONTROL THE SOLDER THICKNESS FOR DOUBLE SIDED COOLING POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/226119 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226119
Method and structure to control the solder thickness for double sided cooling power module Jul 24, 2023 Issued
Array ( [id] => 18789501 [patent_doc_number] => 20230378175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICES HAVING FINS AND AN ISOLATION REGION [patent_app_type] => utility [patent_app_number] => 18/358594 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358594
Semiconductor devices having fins and multiple isolation regions Jul 24, 2023 Issued
Array ( [id] => 18774358 [patent_doc_number] => 20230369189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => STACKED VIA STRUCTURE DISPOSED ON A CONDUCTIVE PILLAR OF A SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 18/357987 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357987
Stacked via structure disposed on a conductive pillar of a semiconductor die Jul 23, 2023 Issued
Array ( [id] => 19238179 [patent_doc_number] => 20240195374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHOD FOR VARYING AMPLIFIER GAIN [patent_app_type] => utility [patent_app_number] => 18/356478 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356478
METHOD FOR VARYING AMPLIFIER GAIN Jul 20, 2023 Pending
Array ( [id] => 19252858 [patent_doc_number] => 20240203855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/356721 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356721
SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME Jul 20, 2023 Pending
Array ( [id] => 18757523 [patent_doc_number] => 20230360986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER [patent_app_type] => utility [patent_app_number] => 18/352271 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352271
Semiconductor structure having an anti-arcing pattern disposed on a passivation layer Jul 13, 2023 Issued
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