
Khiem D. Nguyen
Examiner (ID: 4456)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2892, 2842, 2843, 4146, 2823, 2817 |
| Total Applications | 2760 |
| Issued Applications | 2233 |
| Pending Applications | 206 |
| Abandoned Applications | 396 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19237434
[patent_doc_number] => 20240194629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach
[patent_app_type] => utility
[patent_app_number] => 18/351369
[patent_app_country] => US
[patent_app_date] => 2023-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7030
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351369
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/351369 | Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach | Jul 11, 2023 | Pending |
Array
(
[id] => 18743454
[patent_doc_number] => 20230352442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => Process Including a Re-etching Process for Forming a Semiconductor Structure
[patent_app_type] => utility
[patent_app_number] => 18/349696
[patent_app_country] => US
[patent_app_date] => 2023-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7879
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349696
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/349696 | Semiconductor structure having a conductive feature comprising an adhesion layer and a metal region over and contacting the adhesion layer | Jul 9, 2023 | Issued |
Array
(
[id] => 18758264
[patent_doc_number] => 20230361735
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => COMMON ADJUSTMENT CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/344482
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8605
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344482
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344482 | COMMON ADJUSTMENT CIRCUIT | Jun 28, 2023 | Pending |
Array
(
[id] => 18991224
[patent_doc_number] => 20240063193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/210958
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19789
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210958
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/210958 | SEMICONDUCTOR PACKAGE | Jun 15, 2023 | Pending |
Array
(
[id] => 18712891
[patent_doc_number] => 20230335524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL
[patent_app_type] => utility
[patent_app_number] => 18/334280
[patent_app_country] => US
[patent_app_date] => 2023-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334280
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/334280 | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal | Jun 12, 2023 | Issued |
Array
(
[id] => 18679993
[patent_doc_number] => 20230317651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => PREVENTION OF METAL PAD CORROSION DUE TO EXPOSURE TO HALOGEN
[patent_app_type] => utility
[patent_app_number] => 18/329128
[patent_app_country] => US
[patent_app_date] => 2023-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329128
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/329128 | Semiconductor device having a metal pad and a protective layer for corrosion prevention due to exposure to halogen | Jun 4, 2023 | Issued |
Array
(
[id] => 19101097
[patent_doc_number] => 20240120325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/203668
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9674
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203668
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/203668 | STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | May 30, 2023 | Pending |
Array
(
[id] => 18866673
[patent_doc_number] => 20230421110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => ANALOG PREDISTORTION (APD) SYSTEM FOR POWER AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/203831
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4159
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203831
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/203831 | ANALOG PREDISTORTION (APD) SYSTEM FOR POWER AMPLIFIERS | May 30, 2023 | Pending |
Array
(
[id] => 19469103
[patent_doc_number] => 20240322773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => MULTI-STAGE, FULLY-DIFFERENTIAL CLASS-AB AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 18/202679
[patent_app_country] => US
[patent_app_date] => 2023-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8008
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/202679 | MULTI-STAGE, FULLY-DIFFERENTIAL CLASS-AB AMPLIFIER | May 25, 2023 | Pending |
Array
(
[id] => 19237368
[patent_doc_number] => 20240194563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING SAME
[patent_app_type] => utility
[patent_app_number] => 18/201466
[patent_app_country] => US
[patent_app_date] => 2023-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5842
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201466 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING SAME | May 23, 2023 | Pending |
Array
(
[id] => 18774351
[patent_doc_number] => 20230369182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => FLIP CHIP SELF-ALIGNMENT FEATURES FOR SUBSTRATE AND LEADFRAME APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 18/200130
[patent_app_country] => US
[patent_app_date] => 2023-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4360
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200130
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/200130 | Flip chip self-alignment features for substrate and leadframe applications and method of manufacturing the flip chip self-alignment features | May 21, 2023 | Issued |
Array
(
[id] => 19376676
[patent_doc_number] => 12068256
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-20
[patent_title] => Method of manufacturing a three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
[patent_app_type] => utility
[patent_app_number] => 18/319765
[patent_app_country] => US
[patent_app_date] => 2023-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 24
[patent_no_of_words] => 6169
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/319765 | Method of manufacturing a three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate | May 17, 2023 | Issued |
Array
(
[id] => 19589829
[patent_doc_number] => 20240387386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => INTERPOSER HAVING FIRST AND SECOND REDISTRIBUTION LAYERS AND METHODS OF MAKING AND USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/317121
[patent_app_country] => US
[patent_app_date] => 2023-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317121
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/317121 | INTERPOSER HAVING FIRST AND SECOND REDISTRIBUTION LAYERS AND METHODS OF MAKING AND USING THE SAME | May 14, 2023 | Pending |
Array
(
[id] => 18758253
[patent_doc_number] => 20230361724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => SYSTEMS AND METHODS FOR FRONT-END MODULE FILTERING
[patent_app_type] => utility
[patent_app_number] => 18/143168
[patent_app_country] => US
[patent_app_date] => 2023-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143168
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/143168 | SYSTEMS AND METHODS FOR FRONT-END MODULE FILTERING | May 3, 2023 | Pending |
Array
(
[id] => 18848868
[patent_doc_number] => 20230411272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/311898
[patent_app_country] => US
[patent_app_date] => 2023-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9850
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311898
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/311898 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF | May 3, 2023 | Pending |
Array
(
[id] => 20111975
[patent_doc_number] => 12362715
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Voltage controlled attenuator
[patent_app_type] => utility
[patent_app_number] => 18/141947
[patent_app_country] => US
[patent_app_date] => 2023-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 2246
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141947
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/141947 | Voltage controlled attenuator | Apr 30, 2023 | Issued |
Array
(
[id] => 20346071
[patent_doc_number] => 12469806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Semiconductor structure having dielectric plugs penetrating through a polymer layer
[patent_app_type] => utility
[patent_app_number] => 18/308883
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 2243
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308883
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/308883 | Semiconductor structure having dielectric plugs penetrating through a polymer layer | Apr 27, 2023 | Issued |
Array
(
[id] => 18570622
[patent_doc_number] => 20230260959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-17
[patent_title] => METHOD FOR MANUFACTURING COMPOSITE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/140206
[patent_app_country] => US
[patent_app_date] => 2023-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7015
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140206
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/140206 | METHOD FOR MANUFACTURING COMPOSITE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | Apr 26, 2023 | Pending |
Array
(
[id] => 19547251
[patent_doc_number] => 20240364287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => STRUCTURE WITH DIFFERENTIAL AMPLIFIERS HAVING INPUT OFFSET AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 18/306311
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5558
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306311
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306311 | STRUCTURE WITH DIFFERENTIAL AMPLIFIERS HAVING INPUT OFFSET AND RELATED METHODS | Apr 24, 2023 | Pending |
Array
(
[id] => 18730090
[patent_doc_number] => 20230344388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => POWER LIMITING FOR AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/302219
[patent_app_country] => US
[patent_app_date] => 2023-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11584
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302219
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/302219 | POWER LIMITING FOR AMPLIFIERS | Apr 17, 2023 | Pending |