Search

Khiem D. Nguyen

Examiner (ID: 4456)

Most Active Art Unit
2823
Art Unit(s)
2892, 2842, 2843, 4146, 2823, 2817
Total Applications
2760
Issued Applications
2233
Pending Applications
206
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19131632 [patent_doc_number] => 20240136985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => BIAS CIRCUIT AND POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/109876 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109876
Bias circuit and power amplifier Feb 14, 2023 Issued
Array ( [id] => 19131632 [patent_doc_number] => 20240136985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => BIAS CIRCUIT AND POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/109876 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109876
Bias circuit and power amplifier Feb 14, 2023 Issued
Array ( [id] => 19306912 [patent_doc_number] => 20240235492 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => FULLY INTEGRATED CMOS MULTIPLE MOSFET-STACKED DOUBLE PUSH-PULL RF POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/109877 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109877
FULLY INTEGRATED CMOS MULTIPLE MOSFET-STACKED DOUBLE PUSH-PULL RF POWER AMPLIFIER Feb 14, 2023 Pending
Array ( [id] => 19385478 [patent_doc_number] => 20240275348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Two-Stage Circuit With Power Supply Rejection Filter [patent_app_type] => utility [patent_app_number] => 18/110295 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110295
Two-Stage Circuit With Power Supply Rejection Filter Feb 14, 2023 Pending
Array ( [id] => 19306912 [patent_doc_number] => 20240235492 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => FULLY INTEGRATED CMOS MULTIPLE MOSFET-STACKED DOUBLE PUSH-PULL RF POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/109877 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109877
FULLY INTEGRATED CMOS MULTIPLE MOSFET-STACKED DOUBLE PUSH-PULL RF POWER AMPLIFIER Feb 14, 2023 Pending
Array ( [id] => 19007840 [patent_doc_number] => 20240071911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR DEVICE HAVING INDUCTOR AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 18/162071 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162071
SEMICONDUCTOR DEVICE HAVING INDUCTOR AND METHOD OF MANUFACTURING THEREOF Jan 30, 2023 Pending
Array ( [id] => 20389302 [patent_doc_number] => 12489037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor package substrate with a smooth groove straddling topside and sidewall [patent_app_type] => utility [patent_app_number] => 18/104278 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 1229 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104278
Semiconductor package substrate with a smooth groove straddling topside and sidewall Jan 30, 2023 Issued
Array ( [id] => 18821881 [patent_doc_number] => 20230396222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => VARIABLE GAIN AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/102184 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102184
VARIABLE GAIN AMPLIFIER Jan 26, 2023 Pending
Array ( [id] => 20360590 [patent_doc_number] => 12476598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Intrinsic MOS cascode differential input pair [patent_app_type] => utility [patent_app_number] => 18/160546 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2107 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160546
Intrinsic MOS cascode differential input pair Jan 26, 2023 Issued
Array ( [id] => 20375752 [patent_doc_number] => 12483197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Amplifier circuit [patent_app_type] => utility [patent_app_number] => 18/158155 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158155
Amplifier circuit Jan 22, 2023 Issued
Array ( [id] => 19335645 [patent_doc_number] => 20240250075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => INTEGRATED POWER MODULE PACKAGE OPENING WITH EXPOSED COMPONENT [patent_app_type] => utility [patent_app_number] => 18/156449 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156449
INTEGRATED POWER MODULE PACKAGE OPENING WITH EXPOSED COMPONENT Jan 18, 2023 Pending
Array ( [id] => 19322154 [patent_doc_number] => 20240243701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => AMPLIFIER CIRCUIT FOR BUFFERING HIGH SLEW RATE SIGNAL [patent_app_type] => utility [patent_app_number] => 18/098264 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098264
AMPLIFIER CIRCUIT FOR BUFFERING HIGH SLEW RATE SIGNAL Jan 17, 2023 Pending
Array ( [id] => 18380471 [patent_doc_number] => 20230155561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/155267 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155267
Semiconductor device Jan 16, 2023 Issued
Array ( [id] => 18380463 [patent_doc_number] => 20230155553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => LOW POWER OPERATIONAL AMPLIFIER TRIM OFFSET CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/155261 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155261 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155261
Low power operational amplifier trim offset circuitry Jan 16, 2023 Issued
Array ( [id] => 18541497 [patent_doc_number] => 20230246613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => AMPLIFIER AND METHOD FOR CONTROLLING COMMON MODE VOLTAGE OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/154822 [patent_app_country] => US [patent_app_date] => 2023-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154822
AMPLIFIER AND METHOD FOR CONTROLLING COMMON MODE VOLTAGE OF THE SAME Jan 13, 2023 Pending
Array ( [id] => 18410609 [patent_doc_number] => 20230171962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material [patent_app_type] => utility [patent_app_number] => 18/096341 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096341
Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material Jan 11, 2023 Issued
Array ( [id] => 18514689 [patent_doc_number] => 20230230950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SELF-DENSIFYING NANO-SILVER PASTE AND A METHOD OF FORMING INTERCONNECT LAYER FOR HIGH POWER ELECTRONICS [patent_app_type] => utility [patent_app_number] => 18/154033 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154033
SELF-DENSIFYING NANO-SILVER PASTE AND A METHOD OF FORMING INTERCONNECT LAYER FOR HIGH POWER ELECTRONICS Jan 11, 2023 Pending
Array ( [id] => 19116481 [patent_doc_number] => 20240128231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => Semiconductor Devices and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 18/149935 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149935
Semiconductor Devices and Methods of Manufacture Jan 3, 2023 Pending
Array ( [id] => 18349689 [patent_doc_number] => 20230137800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/090918 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090918
Semiconductor package having a semiconductor element and a wiring structure Dec 28, 2022 Issued
Array ( [id] => 19063639 [patent_doc_number] => 11942902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Methods related to power amplification systems with adjustable common base bias [patent_app_type] => utility [patent_app_number] => 18/090441 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090441
Methods related to power amplification systems with adjustable common base bias Dec 27, 2022 Issued
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