Search

Khiem D. Nguyen

Examiner (ID: 3485, Phone: (571)270-3941 , Office: P/2842 )

Most Active Art Unit
2823
Art Unit(s)
2817, 2843, 4146, 2823, 2892, 2842
Total Applications
2858
Issued Applications
2312
Pending Applications
190
Abandoned Applications
403

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18712891 [patent_doc_number] => 20230335524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL [patent_app_type] => utility [patent_app_number] => 18/334280 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334280
Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal Jun 12, 2023 Issued
Array ( [id] => 19635352 [patent_doc_number] => 20240413801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => VOLTAGE-MODE FILTERS WITH OUTPUT IMPEDANCE NEUTRALIZATION [patent_app_type] => utility [patent_app_number] => 18/330429 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330429
VOLTAGE-MODE FILTERS WITH OUTPUT IMPEDANCE NEUTRALIZATION Jun 6, 2023 Pending
Array ( [id] => 18679993 [patent_doc_number] => 20230317651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => PREVENTION OF METAL PAD CORROSION DUE TO EXPOSURE TO HALOGEN [patent_app_type] => utility [patent_app_number] => 18/329128 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329128
Semiconductor device having a metal pad and a protective layer for corrosion prevention due to exposure to halogen Jun 4, 2023 Issued
Array ( [id] => 18866673 [patent_doc_number] => 20230421110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ANALOG PREDISTORTION (APD) SYSTEM FOR POWER AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 18/203831 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203831
ANALOG PREDISTORTION (APD) SYSTEM FOR POWER AMPLIFIERS May 30, 2023 Pending
Array ( [id] => 20566237 [patent_doc_number] => 12568864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Stacked package structure including a chip disposed on a redistribution layer and a molding layer comprises a recess [patent_app_type] => utility [patent_app_number] => 18/203668 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4488 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203668
Stacked package structure including a chip disposed on a redistribution layer and a molding layer comprises a recess May 30, 2023 Issued
Array ( [id] => 19469103 [patent_doc_number] => 20240322773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MULTI-STAGE, FULLY-DIFFERENTIAL CLASS-AB AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/202679 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202679
Multi-stage, fully-differential class-AB amplifier May 25, 2023 Issued
Array ( [id] => 19054808 [patent_doc_number] => 20240096777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/323646 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323646
SEMICONDUCTOR PACKAGE May 24, 2023 Pending
Array ( [id] => 19237368 [patent_doc_number] => 20240194563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 18/201466 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201466
Semiconductor package including a plurality of heat dissipation reinforcements and method for fabricating same May 23, 2023 Issued
Array ( [id] => 20884787 [patent_doc_number] => 12700835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Hybrid class-D amplifier [patent_app_type] => utility [patent_app_number] => 18/200593 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200593
HYBRID CLASS-D AMPLIFIER May 22, 2023 Pending
Array ( [id] => 18774351 [patent_doc_number] => 20230369182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => FLIP CHIP SELF-ALIGNMENT FEATURES FOR SUBSTRATE AND LEADFRAME APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/200130 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200130
Flip chip self-alignment features for substrate and leadframe applications and method of manufacturing the flip chip self-alignment features May 21, 2023 Issued
Array ( [id] => 19376676 [patent_doc_number] => 12068256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Method of manufacturing a three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate [patent_app_type] => utility [patent_app_number] => 18/319765 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 6169 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319765 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319765
Method of manufacturing a three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate May 17, 2023 Issued
Array ( [id] => 19589783 [patent_doc_number] => 20240387340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => Through-Hole Structures for Improved Power Performance [patent_app_type] => utility [patent_app_number] => 18/318755 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318755
Through-Hole Structures for Improved Power Performance May 16, 2023 Pending
Array ( [id] => 19589829 [patent_doc_number] => 20240387386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => INTERPOSER HAVING FIRST AND SECOND REDISTRIBUTION LAYERS AND METHODS OF MAKING AND USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/317121 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317121
INTERPOSER HAVING FIRST AND SECOND REDISTRIBUTION LAYERS AND METHODS OF MAKING AND USING THE SAME May 14, 2023 Pending
Array ( [id] => 18758253 [patent_doc_number] => 20230361724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SYSTEMS AND METHODS FOR FRONT-END MODULE FILTERING [patent_app_type] => utility [patent_app_number] => 18/143168 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143168
SYSTEMS AND METHODS FOR FRONT-END MODULE FILTERING May 3, 2023 Pending
Array ( [id] => 18848868 [patent_doc_number] => 20230411272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/311898 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311898
ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF May 3, 2023 Pending
Array ( [id] => 20111975 [patent_doc_number] => 12362715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Voltage controlled attenuator [patent_app_type] => utility [patent_app_number] => 18/141947 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2246 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141947
Voltage controlled attenuator Apr 30, 2023 Issued
Array ( [id] => 20346071 [patent_doc_number] => 12469806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor structure having dielectric plugs penetrating through a polymer layer [patent_app_type] => utility [patent_app_number] => 18/308883 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 2243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308883
Semiconductor structure having dielectric plugs penetrating through a polymer layer Apr 27, 2023 Issued
Array ( [id] => 20868517 [patent_doc_number] => 12695426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Temperature correction for radio-frequency circuits [patent_app_type] => utility [patent_app_number] => 18/141205 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141205
TEMPERATURE CORRECTION FOR RADIO-FREQUENCY CIRCUITS Apr 27, 2023 Issued
Array ( [id] => 20792907 [patent_doc_number] => 12666840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Display panel, display assembly, and method of operating display panel [patent_app_type] => utility [patent_app_number] => 18/689335 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18689335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/689335
Display panel, display assembly, and method of operating display panel Apr 26, 2023 Issued
Array ( [id] => 18570622 [patent_doc_number] => 20230260959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => METHOD FOR MANUFACTURING COMPOSITE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/140206 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140206
METHOD FOR MANUFACTURING COMPOSITE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Apr 26, 2023 Pending
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