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Khurram Sajjad

Examiner (ID: 12569)

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
4
Issued Applications
1
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19046675 [patent_doc_number] => 11935795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Method for forming a crystalline protective polysilicon layer [patent_app_type] => utility [patent_app_number] => 17/876442 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876442
Method for forming a crystalline protective polysilicon layer Jul 27, 2022 Issued
Array ( [id] => 17993185 [patent_doc_number] => 20220359222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => DOUBLE PATTERNING METHOD [patent_app_type] => utility [patent_app_number] => 17/874371 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874371
Double patterning method Jul 26, 2022 Issued
Array ( [id] => 18024257 [patent_doc_number] => 20220375756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Germanium Hump Reduction [patent_app_type] => utility [patent_app_number] => 17/814283 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814283
Germanium hump reduction Jul 21, 2022 Issued
Array ( [id] => 18008411 [patent_doc_number] => 20220367178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SPIN ON CARBON COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/864293 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864293
Spin on carbon composition and method of manufacturing a semiconductor device Jul 12, 2022 Issued
Array ( [id] => 17949475 [patent_doc_number] => 20220336494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Integrated Assemblies and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 17/854393 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854393
Integrated assemblies and methods of forming integrated assemblies Jun 29, 2022 Issued
Array ( [id] => 17900854 [patent_doc_number] => 20220310516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 17/841479 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841479
CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Jun 14, 2022 Pending
Array ( [id] => 18840153 [patent_doc_number] => 11848232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Method for Si gap fill by PECVD [patent_app_type] => utility [patent_app_number] => 17/839170 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839170
Method for Si gap fill by PECVD Jun 12, 2022 Issued
Array ( [id] => 17886441 [patent_doc_number] => 20220301919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => Fan-Out Interconnect Structure and Methods Forming the Same [patent_app_type] => utility [patent_app_number] => 17/805557 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805557
Fan-Out Interconnect Structure and Methods Forming the Same Jun 5, 2022 Pending
Array ( [id] => 17886383 [patent_doc_number] => 20220301861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/832675 [patent_app_country] => US [patent_app_date] => 2022-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832675
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME Jun 4, 2022 Pending
Array ( [id] => 18985402 [patent_doc_number] => 11910612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array [patent_app_type] => utility [patent_app_number] => 17/804986 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 60 [patent_no_of_words] => 11196 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804986
Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array May 31, 2022 Issued
Array ( [id] => 18950964 [patent_doc_number] => 11894270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Grating replication using helmets and topographically-selective deposition [patent_app_type] => utility [patent_app_number] => 17/720152 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 10887 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720152
Grating replication using helmets and topographically-selective deposition Apr 12, 2022 Issued
Array ( [id] => 17738250 [patent_doc_number] => 20220223712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/709264 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709264
Semiconductor device and manufacturing method for the semiconductor device Mar 29, 2022 Issued
Array ( [id] => 18797100 [patent_doc_number] => 11830937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/700034 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 8942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700034
Method of manufacturing a semiconductor device and a semiconductor device Mar 20, 2022 Issued
Array ( [id] => 18562979 [patent_doc_number] => 11728232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor package having a stiffener ring [patent_app_type] => utility [patent_app_number] => 17/685303 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 8433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685303
Semiconductor package having a stiffener ring Mar 1, 2022 Issued
Array ( [id] => 17660737 [patent_doc_number] => 20220181202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEME [patent_app_type] => utility [patent_app_number] => 17/682234 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682234
AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEME Feb 27, 2022 Pending
Array ( [id] => 18999277 [patent_doc_number] => 11916133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Self-aligned contact structures [patent_app_type] => utility [patent_app_number] => 17/676699 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 11336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676699
Self-aligned contact structures Feb 20, 2022 Issued
Array ( [id] => 17645353 [patent_doc_number] => 20220173092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Hybrid Bonding with Uniform Pattern Density [patent_app_type] => utility [patent_app_number] => 17/651881 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/651881
Hybrid bonding with uniform pattern density Feb 20, 2022 Issued
Array ( [id] => 18704875 [patent_doc_number] => 11791393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/579613 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579613
Semiconductor device and method of forming the same Jan 19, 2022 Issued
Array ( [id] => 18347045 [patent_doc_number] => 20230135155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => Atomic Layer Etching to Reduce Pattern Loading in High-K Dielectric Layer [patent_app_type] => utility [patent_app_number] => 17/648431 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648431
Atomic Layer Etching to Reduce Pattern Loading in High-K Dielectric Layer Jan 19, 2022 Pending
Array ( [id] => 17582850 [patent_doc_number] => 20220139705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD OF FORMING OXIDE LAYER AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/648420 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648420
METHOD OF FORMING OXIDE LAYER AND SEMICONDUCTOR STRUCTURE Jan 18, 2022 Pending
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