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Khurram Sajjad

Examiner (ID: 12569)

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
4
Issued Applications
1
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17373758 [patent_doc_number] => 20220028810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/398127 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398127
Semiconductor structure and method for forming semiconductor structure Aug 9, 2021 Issued
Array ( [id] => 17295330 [patent_doc_number] => 20210391169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => METHOD FOR FORMING SILICON DIOXIDE FILM AND METHOD FOR FORMING METAL GATE [patent_app_type] => utility [patent_app_number] => 17/398075 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398075
Method for forming silicon dioxide film and method for forming metal gate Aug 9, 2021 Issued
Array ( [id] => 17963572 [patent_doc_number] => 20220344153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/397482 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397482
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Aug 8, 2021 Pending
Array ( [id] => 19244480 [patent_doc_number] => 12014932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Memory, substrate structure of the memory, and method for preparing the substrate structure of the memory [patent_app_type] => utility [patent_app_number] => 17/396690 [patent_app_country] => US [patent_app_date] => 2021-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5159 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396690
Memory, substrate structure of the memory, and method for preparing the substrate structure of the memory Aug 6, 2021 Issued
Array ( [id] => 17247160 [patent_doc_number] => 20210366905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/393025 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393025
Semiconductor device and method for fabricating the same Aug 2, 2021 Issued
Array ( [id] => 17232256 [patent_doc_number] => 20210358813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => Forming a Protective Layer to Prevent Formation of Leakage Paths [patent_app_type] => utility [patent_app_number] => 17/387447 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387447
Forming a Protective Layer to Prevent Formation of Leakage Paths Jul 27, 2021 Pending
Array ( [id] => 19093922 [patent_doc_number] => 11955387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Method of fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/386323 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5575 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386323
Method of fabricating a semiconductor device Jul 26, 2021 Issued
Array ( [id] => 17217856 [patent_doc_number] => 20210351194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => MANUFACTURING METHOD FOR MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/381202 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381202
Manufacturing method for memory structure Jul 20, 2021 Issued
Array ( [id] => 17203798 [patent_doc_number] => 20210343893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => GROUP III NITRIDE BASED LED STRUCTURES INCLUDING MULTIPLE QUANTUM WELLS WITH BARRIER-WELL UNIT INTERFACE LAYERS [patent_app_type] => utility [patent_app_number] => 17/377833 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377833
GROUP III NITRIDE BASED LED STRUCTURES INCLUDING MULTIPLE QUANTUM WELLS WITH BARRIER-WELL UNIT INTERFACE LAYERS Jul 15, 2021 Pending
Array ( [id] => 17389293 [patent_doc_number] => 20220037145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SILICON NITRIDE FILMS HAVING REDUCED INTERFACIAL STRAIN [patent_app_type] => utility [patent_app_number] => 17/377135 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377135
SILICON NITRIDE FILMS HAVING REDUCED INTERFACIAL STRAIN Jul 14, 2021 Pending
Array ( [id] => 18431795 [patent_doc_number] => 11677027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/371953 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 10897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371953
Semiconductor device and method Jul 8, 2021 Issued
Array ( [id] => 19244540 [patent_doc_number] => 12014995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Warpage-reducing semiconductor structure and fabricating method of the same [patent_app_type] => utility [patent_app_number] => 17/369936 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369936
Warpage-reducing semiconductor structure and fabricating method of the same Jul 6, 2021 Issued
Array ( [id] => 17509182 [patent_doc_number] => 20220102285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CMP SAFE ALIGNMENT MARK [patent_app_type] => utility [patent_app_number] => 17/369841 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369841
CMP SAFE ALIGNMENT MARK Jul 6, 2021 Pending
Array ( [id] => 17373635 [patent_doc_number] => 20220028687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD OF DEPOSITING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/360982 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360982
Method of depositing thin film and method of manufacturing semiconductor device using the same Jun 27, 2021 Issued
Array ( [id] => 18097307 [patent_doc_number] => 20220415648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SELECTIVE CARBON DEPOSITION ON TOP AND BOTTOM SURFACES OF SEMICONDUCTOR SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/359947 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359947
SELECTIVE CARBON DEPOSITION ON TOP AND BOTTOM SURFACES OF SEMICONDUCTOR SUBSTRATES Jun 27, 2021 Pending
Array ( [id] => 17795548 [patent_doc_number] => 20220254640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => Amorphous Silicon-Based Scavenging And Sealing EOT [patent_app_type] => utility [patent_app_number] => 17/347786 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347786
Amorphous Silicon-Based Scavenging And Sealing EOT Jun 14, 2021 Pending
Array ( [id] => 17901152 [patent_doc_number] => 20220310814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Conductive Capping For Work Function Layer and Method Forming Same [patent_app_type] => utility [patent_app_number] => 17/340818 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340818
Conductive Capping For Work Function Layer and Method Forming Same Jun 6, 2021 Pending
Array ( [id] => 17855485 [patent_doc_number] => 20220285528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => FORMATION OF TRANSISTOR GATES [patent_app_type] => utility [patent_app_number] => 17/340037 [patent_app_country] => US [patent_app_date] => 2021-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340037
Formation of transistor gates Jun 5, 2021 Issued
Array ( [id] => 17765084 [patent_doc_number] => 20220238697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Reducing K Values of Dielectric Films Through Anneal [patent_app_type] => utility [patent_app_number] => 17/333592 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333592
Reducing K Values of Dielectric Films Through Anneal May 27, 2021 Pending
Array ( [id] => 18447059 [patent_doc_number] => 11682635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Systems and methods for the use of fraud prevention fluid to prevent chip fraud [patent_app_type] => utility [patent_app_number] => 17/327152 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/327152
Systems and methods for the use of fraud prevention fluid to prevent chip fraud May 20, 2021 Issued
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