Search

Kibrom K. Gebresilassie

Examiner (ID: 3051, Phone: (571)272-8571 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2148, 2129, 2128, 2189
Total Applications
819
Issued Applications
542
Pending Applications
82
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4761345 [patent_doc_number] => 20080313571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'METHOD AND SYSTEM FOR AUTOMATING THE CREATION OF CUSTOMER-CENTRIC INTERFACES' [patent_app_type] => utility [patent_app_number] => 12/127403 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313571.pdf [firstpage_image] =>[orig_patent_app_number] => 12127403 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127403
Method and system for automating the creation of customer-centric interfaces May 26, 2008 Issued
Array ( [id] => 4448588 [patent_doc_number] => 07865340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Probabilistic regression suites for functional verification' [patent_app_type] => utility [patent_app_number] => 12/121962 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10426 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865340.pdf [firstpage_image] =>[orig_patent_app_number] => 12121962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121962
Probabilistic regression suites for functional verification May 15, 2008 Issued
Array ( [id] => 5362367 [patent_doc_number] => 20090037161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Methods for improved simulation of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/082971 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037161.pdf [firstpage_image] =>[orig_patent_app_number] => 12082971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/082971
Methods for improved simulation of integrated circuit designs Apr 13, 2008 Issued
Array ( [id] => 5570952 [patent_doc_number] => 20090254331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'COMPACT CIRCUIT-SIMULATION OUTPUT' [patent_app_type] => utility [patent_app_number] => 12/060984 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4669 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20090254331.pdf [firstpage_image] =>[orig_patent_app_number] => 12060984 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060984
Compact circuit-simulation output Apr 1, 2008 Issued
Array ( [id] => 5475612 [patent_doc_number] => 20090248778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SYSTEMS AND METHODS FOR A COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX' [patent_app_type] => utility [patent_app_number] => 12/057693 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6216 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20090248778.pdf [firstpage_image] =>[orig_patent_app_number] => 12057693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/057693
Systems and methods for a combined matrix-vector and matrix transpose vector multiply for a block-sparse matrix Mar 27, 2008 Issued
Array ( [id] => 8119243 [patent_doc_number] => 08160841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Bridge information modeling' [patent_app_type] => utility [patent_app_number] => 12/055961 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/160/08160841.pdf [firstpage_image] =>[orig_patent_app_number] => 12055961 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055961
Bridge information modeling Mar 25, 2008 Issued
Array ( [id] => 4766305 [patent_doc_number] => 20080177517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/055852 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3211 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177517.pdf [firstpage_image] =>[orig_patent_app_number] => 12055852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055852
TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS Mar 25, 2008 Abandoned
Array ( [id] => 8984597 [patent_doc_number] => 08515727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Automatic logic model build process with autonomous quality checking' [patent_app_type] => utility [patent_app_number] => 12/051288 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3406 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12051288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051288
Automatic logic model build process with autonomous quality checking Mar 18, 2008 Issued
Array ( [id] => 4699670 [patent_doc_number] => 20080221854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'COMPUTER AIDED DESIGN APPARATUS, COMPUTER AIDED DESIGN PROGRAM, COMPUTER AIDED DESIGN METHOD FOR A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR CIRCUIT BASED ON CHARACTERISTIC VALUE AND SIMULATION PARAMETER' [patent_app_type] => utility [patent_app_number] => 12/042059 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13485 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20080221854.pdf [firstpage_image] =>[orig_patent_app_number] => 12042059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042059
Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter Mar 3, 2008 Issued
Array ( [id] => 4729067 [patent_doc_number] => 20080208555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'SIMULATION METHOD AND SIMULATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/037297 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4594 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20080208555.pdf [firstpage_image] =>[orig_patent_app_number] => 12037297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037297
Simulation method and simulation apparatus Feb 25, 2008 Issued
Array ( [id] => 8388511 [patent_doc_number] => 08265917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-11 [patent_title] => 'Co-simulation synchronization interface for IC modeling' [patent_app_type] => utility [patent_app_number] => 12/036895 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12036895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036895
Co-simulation synchronization interface for IC modeling Feb 24, 2008 Issued
Array ( [id] => 4599903 [patent_doc_number] => 07983880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-19 [patent_title] => 'Simultaneous switching noise analysis using superposition techniques' [patent_app_type] => utility [patent_app_number] => 12/034400 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983880.pdf [firstpage_image] =>[orig_patent_app_number] => 12034400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034400
Simultaneous switching noise analysis using superposition techniques Feb 19, 2008 Issued
Array ( [id] => 5447584 [patent_doc_number] => 20090048810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Computer-implemented system and method for assisting in designing resilient member' [patent_app_type] => utility [patent_app_number] => 12/071264 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20090048810.pdf [firstpage_image] =>[orig_patent_app_number] => 12071264 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071264
Computer-implemented system and method for assisting in designing resilient member Feb 18, 2008 Abandoned
Array ( [id] => 6559096 [patent_doc_number] => 20100017191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'MICROCOMPUTER SIMULATOR' [patent_app_type] => utility [patent_app_number] => 12/516472 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5329 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017191.pdf [firstpage_image] =>[orig_patent_app_number] => 12516472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/516472
Microcomputer simulator Feb 14, 2008 Issued
Array ( [id] => 4966374 [patent_doc_number] => 20080109194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'SYSTEM AND METHOD FOR USING MODEL ANALYSIS TO GENERATE DIRECTED TEST VECTORS' [patent_app_type] => utility [patent_app_number] => 11/970897 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5080 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109194.pdf [firstpage_image] =>[orig_patent_app_number] => 11970897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970897
System and method for using model analysis to generate directed test vectors Jan 7, 2008 Issued
Array ( [id] => 5437046 [patent_doc_number] => 20090171633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Computer-aided method for predicting particle uptake by a surface of a moving object' [patent_app_type] => utility [patent_app_number] => 12/006260 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1784 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20090171633.pdf [firstpage_image] =>[orig_patent_app_number] => 12006260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006260
Computer-aided method for predicting particle uptake by a surface of a moving object Dec 30, 2007 Issued
Array ( [id] => 4808630 [patent_doc_number] => 20080172208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'METHOD AND COMPUTER PROGRAM PRODUCT OF COMPUTER AIDED DESIGN OF A PRODUCT COMPRISING A SET OF CONSTRAINED OBJECTS' [patent_app_type] => utility [patent_app_number] => 11/965400 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20080172208.pdf [firstpage_image] =>[orig_patent_app_number] => 11965400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965400
METHOD AND COMPUTER PROGRAM PRODUCT OF COMPUTER AIDED DESIGN OF A PRODUCT COMPRISING A SET OF CONSTRAINED OBJECTS Dec 26, 2007 Abandoned
Array ( [id] => 6526705 [patent_doc_number] => 20100217570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Method for Simulating the Failure Rate of an Electronic Equipment Due to Neutronic Radiation' [patent_app_type] => utility [patent_app_number] => 12/519679 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5695 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20100217570.pdf [firstpage_image] =>[orig_patent_app_number] => 12519679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/519679
Method for Simulating the Failure Rate of an Electronic Equipment Due to Neutronic Radiation Dec 19, 2007 Abandoned
Array ( [id] => 5266400 [patent_doc_number] => 20090119085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD AND SYSTEM FOR MODELING DYNAMIC BEHAVIOR OF A TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/935969 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119085.pdf [firstpage_image] =>[orig_patent_app_number] => 11935969 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935969
Method and system for simulating dynamic behavior of a transistor Nov 5, 2007 Issued
Array ( [id] => 5266857 [patent_doc_number] => 20090119542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'SYSTEM, METHOD, AND PROGRAM PRODUCT FOR SIMULATING TEST EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 11/935220 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119542.pdf [firstpage_image] =>[orig_patent_app_number] => 11935220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935220
SYSTEM, METHOD, AND PROGRAM PRODUCT FOR SIMULATING TEST EQUIPMENT Nov 4, 2007 Abandoned
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