
Kibrom K. Gebresilassie
Examiner (ID: 3051, Phone: (571)272-8571 , Office: P/2128 )
| Most Active Art Unit | 2128 |
| Art Unit(s) | 2148, 2129, 2128, 2189 |
| Total Applications | 819 |
| Issued Applications | 542 |
| Pending Applications | 82 |
| Abandoned Applications | 220 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4761345
[patent_doc_number] => 20080313571
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[patent_title] => 'METHOD AND SYSTEM FOR AUTOMATING THE CREATION OF CUSTOMER-CENTRIC INTERFACES'
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[patent_app_number] => 12/127403
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/127403 | Method and system for automating the creation of customer-centric interfaces | May 26, 2008 | Issued |
Array
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[patent_title] => 'Probabilistic regression suites for functional verification'
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Array
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[patent_title] => 'Methods for improved simulation of integrated circuit designs'
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Array
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[patent_title] => 'COMPACT CIRCUIT-SIMULATION OUTPUT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/060984 | Compact circuit-simulation output | Apr 1, 2008 | Issued |
Array
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[patent_title] => 'SYSTEMS AND METHODS FOR A COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX'
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Array
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Array
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Array
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[patent_doc_number] => 08515727
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[patent_issue_date] => 2013-08-20
[patent_title] => 'Automatic logic model build process with autonomous quality checking'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/051288 | Automatic logic model build process with autonomous quality checking | Mar 18, 2008 | Issued |
Array
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[id] => 4699670
[patent_doc_number] => 20080221854
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[patent_issue_date] => 2008-09-11
[patent_title] => 'COMPUTER AIDED DESIGN APPARATUS, COMPUTER AIDED DESIGN PROGRAM, COMPUTER AIDED DESIGN METHOD FOR A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR CIRCUIT BASED ON CHARACTERISTIC VALUE AND SIMULATION PARAMETER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/042059 | Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter | Mar 3, 2008 | Issued |
Array
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[id] => 4729067
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[patent_title] => 'SIMULATION METHOD AND SIMULATION APPARATUS'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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